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UPD30181A fiches techniques PDF

NEC - 64/32 Bit Microcontroller

Numéro de référence UPD30181A
Description 64/32 Bit Microcontroller
Fabricant NEC 
Logo NEC 





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UPD30181A fiche technique
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30181A, 30181AY
VR4181ATM
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The µPD30181A and 30181AY (VR4181A), which are high-performance 64-/32-bit microprocessors employing the
RISC (reduced instruction set computer) architecture developed by MIPSTM, are products in the VR SeriesTM of
microprocessors manufactured by NEC.
The VR4181A includes as its CPU the VR4120™ core, an ultra-low-power-consumption core featuring cache
memory, a high-speed product-sum operation unit, and a memory management unit. Other on-chip components
include an LCD controller, CompactFlash controller, USB host/function controller, DMA controller, SDRAM controller,
PWM controller, AC97/I2S audio interface, full-duplex asynchronous serial interface, IrDA interface, I2C serial
interface, keyboard interface, touch panel interface, real-time clock, A/D converter, D/A converter, and other
controllers and interfaces required for battery-driven mobile information devices, fixed compact information devices,
car navigation systems, and compact embedded devices.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
VR4181A Hardware User’s Manual (U16049E)
VR4100 SeriesTM Architecture User’s Manual (U15509E)
FEATURES
{ VR4120 core (64-bit RISC core) on chip as CPU
{ Pipeline clock: 131 MHz
{ Conforms to MIPS III (except for FPU, LL and SC
instructions) and MIPS16 instruction sets
{ Supports MACC and DMACC high-speed product-sum
operation instructions
{ On-chip cache memory
Capacity includes 8 KB instruction cache and 8 KB
data cache
{ Employs a writeback cache
{ Physical addresses: 32 bits
Virtual addresses: 40 bits
{ On-chip 32 double-entry TLB
{ Effective power management using four modes:
Fullspeed, Standby, Suspend, and Hibernate
{ Employs a high-performance internal system bus (T-
bus)
{ DRAM controller supporting 64 Mb, 128 Mb, and 256
Mb SDRAMs
{ External system bus interface supporting ROM, page
ROM, flash memory, SRAM, ISA devices, IDE (ATA)
devices, and SyncFlash™ memory
{ UMA type LCD controller (supports STN and TFT
panels)
{ ExCA register-compatible CompactFlash interface (2
slots)
{ USB host controller (Rev1.1, OHCI Rev1.0)
controller
{ USB function (Rev1.1) controller
{ AC97 and I2S audio interfaces (1 channel each)
{ Clocked serial interface (1 channel)
{ NS16550-compatible serial interface (3 channels)
{ IrDA (SIR) interface (1 channel)
{ I2C bus interfaces (2 channels, µPD30181AY only)
{ PWM controller (3 channels)
{ DMA controller supporting chain mode (4 channels)
{ Keyboard scan interface (supports 8 × 12 key matrix)
{ X-Y coordinate auto scan touch panel interface
{ On-chip A/D converter and D/A converter
{ On-chip watchdog timer unit
{ RTC unit (total of 3 timer and counter channels)
{ On-chip PLL and clock generators
{ Power supplies: 2.5 V for core, 3.3 V for I/O block
{ Package: 240-pin plastic FBGA
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U16277EJ1V0DS00 (1st edition)
Date Published October 2002 N CP(K)
Printed in Japan
The mark shows major revised points.
©
©
2002
1997

PagesPages 30
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