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PDF ICX205AK Data sheet ( Hoja de datos )
| Número de pieza | ICX205AK | |
| Descripción | Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor | |
| Fabricantes | Sony | |
| Logotipo |  |
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ICX205AK
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX205AK is a diagonal 8mm (Type 1/2)
interline CCD solid-state image sensor with a square
pixel array and 1.45M effective pixels. Progressive
scan allows all pixels' signals to be output
independently within approximately 1/7.5 second.
Also, the adoption of high frame rate readout mode
supports 30 frames per second. This chip features
an electronic shutter with variable charge-storage
time which makes it possible to realize full-frame still
image without a mechanical shutter. High resolution
and high color reproductivity are achieved through
the use of R, G, B primary color mosaic filters.
Further, high sensitivity and low dark current are
achieved through the adoption of HAD (Hole-
Accumulation Diode) sensors.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
20 pin DIP (Cer-DIP)
Features
• Progressive scan allows individual readout of the
image signals from all pixels.
• High horizontal and vertical resolution (both approx.
800TV-lines) still image without a mechanical shutter.
• Supports high frame rate readout mode
(effective 256 lines output, 30 frame/s)
• Square pixel
• Horizontal drive frequency: 14.318MHz
• No voltage adjustments
(reset gate and substrate bias are not adjusted.)
• R, G, B primary color mosaic filters on chip
• High resolution, high color reproductivity,
high sensitivity, low dark current
• Low smear, excellent antiblooming characteristics
• Continuous variable-speed shutter
Pin 1
V
2
Pin 11
H
40
Optical black position
(Top View)
Device Structure
• Interline CCD image sensor
• Image size:
• Total number of pixels:
• Number of effective pixels:
• Number of active pixels:
• Chip size:
• Unit cell size:
• Optical black:
• Number of dummy bits:
• Substrate material:
Diagonal 8mm (Type 1/2)
1434 (H) × 1050 (V) approx. 1.50M pixels
1392 (H) × 1040 (V) approx. 1.45M pixels
1360 (H) × 1024 (V) approx. 1.40M pixels (7.959mm diagonal)
7.60mm (H) × 6.20mm (V)
4.65µm (H) × 4.65µm (V)
Horizontal (H) direction: Front 2 pixels, rear 40 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
Horizontal 20
Vertical 3
Silicon
2
8
∗ Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98118D3Z
1 page  
ICX205AK
Bias Conditions
Item Symbol Min. Typ. Max. Unit Remarks
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
VDD
VL
φSUB
φRG
14.55
15.0
∗1
∗2
∗2
15.45
V
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min.
IDD
Typ.
5.5
Max.
Unit Remarks
mA
Clock Voltage Conditions
Item Symbol
Readout clock voltage VVT
VVH02A
VVH1, VVH2A,
VVH2B, VVH3
VVL1, VVL2A,
VVL2B, VVL3
Vertical transfer clock
voltage
Vφ1, Vφ2A,
Vφ2B, Vφ3
| VVL1 – VVL3 |
VVHH
VVHL
VVLH
VVLL
Horizontal transfer
clock voltage
VφH
VHL
Reset gate clock
voltage
VφRG
VRGLH – VRGLL
VRGL – VRGLm
Substrate clock voltage VφSUB
Min.
14.55
–0.05
Typ.
15.0
0
Max. Unit
15.45 V
0.05 V
Waveform
diagram
1
2
Remarks
VVH = VVH02A
–0.2 0 0.05 V
2
–8.4 –8.0 –7.6 V
2 VVL = (VVL1 + VVL3)/2
7.6 8.0 8.4 V
0.1
0.9
1.3
1.0
0.9
4.75 5.0 5.25
–0.05 0 0.05
3.0 3.3 5.5
0.4
0.5
22.15 23.0 23.85
V
V
V
V
V
V
V
V
V
V
V
2
2
2 High-level coupling
2 High-level coupling
2 Low-level coupling
2 Low-level coupling
3
3
4
4 Low-level coupling
4 Low-level coupling
5
–5–
5 Page 
ICX205AK
Image Sensor Characteristics Measurement Method
Color coding and readout of this image sensor
Gb B Gb B
R Gr R Gr
Gb B Gb B
R Gr R Gr
The primary color filters of this image sensor are arranged in the layout
shown in the figure on the left (Bayer arrangement).
Gr and Gb denote the G signals on the same line as the R signal and
the B signal, respectively.
Horizontal register
Color Coding Diagram
All pixel signals are output successively in a 1/7.5s period.
The R signal and Gr signal lines and the Gb signal and B signal lines are output successively.
– 11 –
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ICX205AK.PDF ] | |
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