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PDF VSC8201 Data sheet ( Hoja de datos )
| Número de pieza | VSC8201 | |
| Descripción | PCB Design and Layout Guide | |
| Fabricantes | Vitesse | |
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SimpliPHY® VSC8201
PCB Design and Layout Guide
Single Port 10/100/1000BASE-Tand 1000BASE-X PHY
Introduction
This purpose of this application note in conjunction with the VSC8201 Datasheet is to provide information to assist in the design and lay-
out of the VSC8201 Gigabit Ethernet Transceiver.
Power Supply Organization and Decoupling
The VSC8201 requires a 3.3v and a 1.5v power supply source for operation using GMII, MII or TBI MAC interfaces. In RGMII and RTBI
modes, an additional 2.5v supply is needed as specified by the RGMI/RTBI standard. The VSC8201 can be powered using the following
options:
• 2 separate supplies, 3.3v and 1.5v respectively.
• A single 3.3v supply. This is done by using the optional on-chip regulator control circuit, which drives a simple external series pass
type supply regulator (MOSFET) to generate the 1.5v core power supply.
PCB Power Plane Organization
It is recommended that the PCB power plane(s) in a system be divided into four separate regions:
Table 1: Power Supply Plane Regions
PCB Power Description
Plane
Nominal
Supply Voltage
Currenta
Typ Max
LQFP Supply Namesb
V+IO
V+A33
V+A15
V+DIG
Digital Input/Output
buffer supply
Filtered analog 3.3v
supply
Filtered analog 1.5v
supply
Digital core supply
3.3v/2.5v
3.3v
1.5v
1.5v
8mA
101mA
41mA
350mA
11mA
111mA
48mA
423mA
VDDIO
TXVDD, VDDREC33,
VDDPLL33
VDDREC15, VDDPLL15
VDDDIG
a. Test conditions: Room temperature (25oC), 1000BASE-T data, full duplex, minimum IPG, 64-byte packets, RGMII MAC active, excluding
regulator power dissipation but including external twisted pair termination; all worst case current figures have all nominal power supplies
scaled by +5%.
b. Refer VSC8201 Datasheet to correlate supply names with part pin numbers.
Power Supply Filtering and Decoupling
For best performance, each power supply region should contain capacitors for both bulk decoupling and for local high-frequency decou-
pling. This is summarized in the following tables:
Rev. 1.6.3 - 9/29/04
VITESSE - CONFIDENTIAL & PROPRIETARY - DO NOT COPY WITHOUT PERMISSION
- Page 1 of 21 -
1 page  
VSC8201DL
Regulator Circuit
For systems with a single power supply, the VSC8201 provides an option to generate the 1.5v supply from the 3.3v supply by using the
on chip regulator. The internal regulator is enabled by having a 10k pull-up on the REG_EN pin.
To use the Regulator the following additional components are required:
• FET device, similar to Fairchild FDT439N.
• For decoupling, two 0.0047uF capacitors with 10% tolerance or better. NPO, X7R or X5R are all acceptable.
Systems with single 3.3v,+/-10% Wake on LAN supply
The following figure shows the circuit for generating the 1.5v supply using a 3.3v,+/-10% supply
Figure 5: Regulator Circuit using 3.3v, +/-10% supply
Key points
• Place a 0.0047uF capacitor as close to REG_OUT as possible.
• Place a 0.0047uF capacitor as close to the FET as possible.
• Tie the GND line together with VREFN, capacitor connected to REF_FILT, resistor R4 (See figure above) and then connect to a com-
mon ground.
• VREFP should be connected to the analog 3.3v plane i.e. V+A33.
Using ActiPHYTM Power Management
The VSC8201 supports a new power saving mode called ActiPHYTM, particularly suited to power saving applications like laptop comput-
ers with wake on LAN capability.1
When in ActiPHYTM mode the PHY is in one of two power down states and has the ability to detect valid signal energy levels at the
media pins and convey it to the station manager.
1. Refer VSC8201 Datasheet.
Rev. 1.6.3 - 9/29/04
VITESSE - CONFIDENTIAL & PROPRIETARY - DO NOT COPY WITHOUT PERMISSION
- Page 5 of 21 -
5 Page 
VSC8201DL
Special RGMII Implementation Using a Single 3.3V Supply
This section addresses designers who wish to use the VSC8201 Single Port Gigabit Ethernet PHY in RGMII interface mode at an inter-
face voltage of 3.3V, rather than the standard1 2.5V.
VSC8201’s RGMII Interface Description
The VSC8201 PHY is designed, as per the RGMII version 1.2a specification, to support RGMII operation at a 2.5v I/O supply. In addition
to the RGMII requirements specified by the standard, the PHY also has an internal clock delay feature (enabled by setting MII Register
23.8) that adds an internal delay of ~2ns to the RXC and the TXC signals when operating at 2.5v. This feature eliminates the need for
PCB trace delays or 2ns buffers in the path of the RXC and TXC traces.
Due to customer interest in using the VSC8201 PHY in RGMII interface mode with a single 3.3v supply, Vitesse has characterized the
RGMII I/O timing of the PHY under this condition in the following two configurations:
• Standard RGMII Implementation (i.e. with RXC and TXC trace delays on the PCB)
• RGMII Implementation using the Internal Clock Delay feature.
Since the VSC8201 PHY was not specifically designed for RGMII operation with a 3.3v I/O supply, certain accommodations must be
made to the board layout in order to ensure a robust interface. The VSC8201 PHY complies with the I/O timing requirements specified in
the RGMII version 1.2a specification. No special board layout considerations other than those mentioned in the standard are required for
this implementation.
RGMII Implementation using the Internal Clock Delay feature with 3.3v I/O Supply
With a 3.3v I/O supply, the worst case internal delay added to the TXC signal is around 3ns. If the TXC, TD[3:0], and TX_CTL traces are
length matched on the PCB, then the PHY may mis-latch data under the worst case TXC delay conditions, resulting in packet errors at
the MAC/PHY transmit interface. Due to this it is important to follow the guidelines mentioned in the section below during board layout.
1. RGMII Version 1.2a
Rev. 1.6.3 - 9/29/04
VITESSE - CONFIDENTIAL & PROPRIETARY - DO NOT COPY WITHOUT PERMISSION
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet VSC8201.PDF ] | |
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