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PDF TC7117 Data sheet ( Hoja de datos )

Número de pieza TC7117
Descripción 3-1/2 Digit Analog-to-Digital Converters with Hold
Fabricantes Microchip 
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TC7116/A/TC7117/A
3-1/2 Digit Analog-to-Digital Converters with Hold
Features:
• Low Temperature Drift Internal Reference:
- TC7116/TC7117 80 ppm/°C, Typ.
- TC7116A/TC7117A 20 ppm/°C, Typ.
• Display Hold Function
• Directly Drives LCD or LED Display
• Zero Reading with Zero Input
• Low Noise for Stable Display:
- 2V or 200mV Full Scale Range (FSR)
• Auto-Zero Cycle Eliminates Need for Zero
• Adjustment Potentiometer
• True Polarity Indication for Precision Null
Applications
• Convenient 9V Battery Operation:
(TC7116/TC7116A)
• High-Impedance CMOS Differential Inputs: 1012Ω
• Low-Power Operation: 10mW
Applications:
• Thermometry
• Bridge Readouts: Strain Gauges, Load Cells,
Null Detectors
• Digital Meters: Voltage/Current/Ohms/Power, pH
• Digital Scales, Process Monitors
• Portable Instrumentation
Device Selection Table
Package Code
Package
Temperature Range
CPL
IJL
CKW
CLW
40-Pin PDIP
40-Pin CERDIP
44-Pin PQFP
44-Pin PLCC
0°C to +70°C
-25°C to +85°C
0°C to +70°C
0°C to +70°C
General Description:
The TC7116A/TC7117A are 3-1/2 digit CMOS Analog-
to-Digital Converters (ADCs) containing all the active
components necessary to construct a 0.05% resolution
measurement system. Seven-segment decoders,
polarity and digit drivers, voltage reference, and clock
circuit are integrated on-chip. The TC7116A drives
Liquid Crystal Displays (LCDs) and includes a back-
plane driver. The TC7117A drives common anode Light
Emitting Diode (LED) displays directly with an 8mA
drive current per segment.
These devices incorporate a display hold (HLDR)
function. The displayed reading remains indefinitely, as
long as HLDR is held high. Conversions continue, but
output data display latches are not updated. The refer-
ence low input (VREF-) is not available, as it is with the
TC7106/7107. VREF- is tied internally to analog
common in the TC7116A/7117A devices.
The TC7116A/7117A reduces linearity error to less
than 1 count. Rollover error (the difference in readings
for equal magnitude but opposite polarity input signals)
is below ±1 count. High-impedance differential inputs
offer 1pA leakage current and a 1012Ω input imped-
ance. The 15μVP-P noise performance enables a “rock
solid” reading. The auto-zero cycle ensures a zero
display reading with a 0V input.
The TC7116A and TC7117A feature a precision, low
drift internal reference, and are functionally identical to
the TC7116/TC7117. A low drift external reference is
not normally required with the TC7116A/TC7117A.
© 2006 Microchip Technology Inc.
DS21457C-page 1

1 page




TC7117 pdf
TC7116/A/TC7117/A
TABLE 1-1: TC7116/A AND TC7117/A ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, specifications apply to both the TC7116/A and TC7117/A at TA = 25°C,
fCLOCK = 48kHz. Parts are tested in the circuit of the Typical Operating Circuit.
Symbol
Parameter
Min
Typ Max Unit
Test Conditions
TCSF Scale Factor Temperature Coefficient
1 5 ppm/°C VIN = 199mV,
“C” Device = 0°C to +70°C
(Ext. Ref = 0ppm°C)
— — 20 ppm/°C “I” Device = -25°C to +85°C
Input Resistance, Pin 1
30 70 — kΩ (Note 5)
VIL, Pin 1
VIL, Pin 1
VIH, Pin 1
V+ - 1.5
IDD Supply Current (Does not Include LED
Current for TC7117/A)
— Test + 1.5 V TC7116/A Only
— GND + 1.5 V TC7117/A Only
— — V Both
0.8 1.8 mA VIN = 0V
VC Analog Common Voltage
(with Respect to Positive Supply)
2.4
3.05
3.35
V 25kΩ Between Common
and Positive Supply
VCTC
Temperature Coefficient of Analog
Common (with Respect to Positive
Supply)
— — — — “C” Device: 0°C to +70°C
20 50 ppm/°C TC7116A/TC7117A
80 — ppm/°C TC7116/TC7117
VSD TC7116/TC7117A ONLY Peak to Peak
Segment Drive Voltage
4
5 6 V V+ to V- = 9V
(Note 4)
VBD TC7116A/TC7116A ONLY Peak to
Peak
Backplane Drive Voltage
4 5 6 V V+ to V- = 9V
(Note 4)
TC7117/TC7117A ONLY
Segment Sinking Current
(Except Pin 19)
5 8 — mA V+ = 5.0V
Segment Voltage = 3V
TC7117/TC7117A ONLY
Segment Sinking Current (Pin 19 Only)
10
16 — mA V+ = 5.0V
Segment Voltage = 3V
Note 1: Input voltages may exceed the supply voltages provided the input current is limited to ±100μA.
2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3: Refer to “Differential Input” discussion.
4: Backplane drive is in phase with segment drive for “OFF” segment, 180° out of phase for “ON” segment. Frequency is
20 times conversion rate. Average DC component is less than 50mV.
5: The TC7116/TC7116A logic inputs have an internal pull-down resistor connected from HLDR, Pin 1 to TEST, Pin 37. The
TC7117/TC7117A logic inputs have an internal pull-down resistor connected from HLDR, Pin 1 to GND, Pin 21.
© 2006 Microchip Technology Inc.
DS21457C-page 5

5 Page





TC7117 arduino
3.2.1 SYSTEM TIMING
The clocking method used for the TC7116/TC7116A
and TC7117/TC7117A is shown in Figure . Three
clocking methods may be used:
1. An external oscillator connected to Pin 40.
2. A crystal between Pins 39 and 40.
3. An RC network using all three pins.
The oscillator frequency is ÷4 before it clocks the
decade counters. It is then further divided to form the
three convert cycle phases: Signal Integrate (1000
counts), Reference De-integrate (0 to 2000 counts),
and Auto-Zero (1000 to 3000 counts). For signals less
than full scale, auto-zero gets the unused portion of ref-
erence de-integrate. This makes a complete measure
cycle of 4000 (16,000 clock pulses), independent of
input voltage. For 3 readings per second, an oscillator
frequency of 48kHz would be used.
TC7116/A/TC7117/A
To achieve maximum rejection of 60Hz pickup, the sig-
nal integrate cycle should be a multiple of 60Hz. Oscil-
lator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
48kHz, 40kHz, etc. should be selected. For 50Hz rejec-
tion, oscillator frequencies of 200kHz, 100kHz,
66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings per second) will reject both
50Hz and 60Hz.
3.2.2 HOLD READING INPUT
When HLDR is at a logic HIGH, the latch will not be
updated. Analog-to-Digital conversions will continue,
but will not be updated until HLDR is returned to LOW.
To continuously update the display, connect to TEST
(TC7116/TC7116A) or GROUND (TC7117/TC7117A),
or disconnect. This input is CMOS compatible with
70kΩ typical resistance to TEST (TC7116/TC7116A) or
GROUND (TC7117/TC7117A).
TC7117
TC7117A
Typical Segment Output
V+
0.5mA
8mA
To
Segment
Digital Ground
Internal Digital Ground
Thousands
To Switch Drivers
From Comparator Output
V+
Clock
÷4
40
OSC1
39
OSC2
38
OSC3
7-Segment 7-Segment 7-Segment
Decode
Decode
Decode
Latch
Hundreds
Tens
Units
Control Logic
1 ~70kΩ
HLDR
35 V+
37
TEST
500Ω
21 Digital
GND
FIGURE 3-6:
TC7117/TC7117A Digital Section
© 2006 Microchip Technology Inc.
DS21457C-page 11

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