PDF NT68F62 Data sheet ( Hoja de datos )

Número de pieza	NT68F62
Descripción	8 Bit Microcontroller for Monitor
Fabricantes	Novatek
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No Preview Available ! .DataSheet4U.com NT68F628-Bit Microcontroller for Monitor (32K Flash MTP Type) wFeatures ww Operating voltage range: 4.5V to 5.5V CMOS technology for low power consumption m6502 8-bit CMOS CPU core 8 MHz operation frequency o32K bytes of flash memory for Multi -Times Program .c512 bytes of RAM 2Kbytes Masked BootROM for ISP. One 8-bit base timer 13 channels of 8-bit PWM outputs with 5V open drain U4 channel A/D converters with 6-bit resolution 25 bi-directional I/O port pins (8 dedicated I/O pins) t4Hsync/Vsync signals processor for separate & composite signals, including hardware sync signals polarity detection and freq. counters with 2 sets of eHsync counting intervals Hsync/Vsync polarity controlled output, 5 selectable efree run output signals and self-test patterns, auto- hmute function, half freq. I/O function Two built-in IIC bus interfaces support VESA DDC1/2B+ taSGeneral Description The NT68F62 is a new generation of monitor µC for auto- async and digital control applications. Particularly, this chip supports various functions to allow users to easily develop USB monitors. It contains the 6502 8-bit CPU core, 512 .Dbytes of RAM for use as working RAM and as stack area, 32K bytes of Flash memory, 13-channels of 8-bit PWM D/A converters, 4-channel A/D converters for detection of keys wwhich can save I/O pins, one 8-bit pre-loadable base timer, an internal Hsync and Vsync signals processor and a watch-dog timer, which prevents the system from abnormal Two layers of interrupt management NMI interrupt sources - INTE0 (External INT with selectable edge trigger) - INTMUTE (Auto Mute Activated) IRQ interrupt sources - INTS0/1 (SCL Go-low INT) - INTA0/1 (Slave Address Matched INT) - INTTX0/1 (Shift Register INT) - INTRX0/1 (Shift Register INT) - INTNAK0/1 (No Acknowledge) - INTSTOP0/1 (Stop Condition Occurred INT) - INTE1 (External INT with Selectable Edge Trigger) - INTV (VSYNC INT) - INTMR (Base Timer INT) - INTADC (AD Conversion Done INT) Hardware watch-dog timer function 40-pin P-DIP and 42-pin S-DIP packages operation and two IIC bus interfaces. The user can store EDID data in the 128 bytes of RAM for DDC1/2B, so that the user can reduce a dedicated EEPROM for EDID. The half frequency output function can save the external one- shot circuit. All of these designs are borne of our committment to offer our user savings on component costs. The 42 pin S-DIP IC provides two additional I/O pins – port40 & port41, Part number NT68F62U represents the S- DIP IC. For future reference, port40 & port42 are only available for the 42 pin S-DIP IC. ww www.DataSheet4U.com1 V1.0 1 page NT68F62 Pin Description (continued) Pin No. 40 Pin 42 Pin Designation 37 39 DAC4/SCL1 Reset Init. DAC4 I/O Description O Open drain 5V, D/A converter output 4, shared with the open drain SCL1 line of IIC bus, Schmitt Trigger buffer 38 40 DAC3 O Open drain 5V, D/A converter output 3 39 41 HSYNCI Debouncing & Schmitt Trigger input pin for video horizontal I sync signal, internal pull high, shared with the composite sync input Debouncing & Schmitt trigger input pin for video vertical 40 42 VSYNCI/INTV VSYNCI I sync signal, internal pull high, shared with the input pin of the external interrupt source, intv, with Schmitt Trigger, selectable triggered and internal pulled up 22KΩ resistor -6 P40 I/O Bi-directional I/O pin with internal pulled up 22KΩ resistor, only 42 pin S-DIP available - 37 P41 I/O Bi-directional I/O pin with internal pulled up 22KΩ resistor, only 42 pin S-DIP available * This RESET pin must be pulled high by an external pulled-up resistor (5KΩ suggestion), or it will remain at low voltage to continually rest system. 5 5 Page NT68F62 System Registers (continued) Addr. $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 Register INIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Control Register for Polling (Read) Interrupt Groups & Clearing (Write) INTE0 & INTMUTE Interrupt Requests NMIPOLL 00H ― ― ― ― ― ― INTE0 INTMUTE ― ― ― ― ― ― CLRE0 CLRMUTE IRQPOLL 00H ― ― ― ― ― IRQ2 IRQ1 IRQ0 Control Registers of Interrupt Enable IENMI 00H ― ― ― ― ― ― INTE0 INTMUTE IEIRQ0 00H ― ― INTS0 INTA0 INTTX0 INTRX0 INTNAK0 INTSTOP0 IEIRQ1 00H ― ― INTS1 INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 IEIRQ2 00H ― ― ― ― INTADC INTV INTE1 INTMR Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests IRQ0 00H ― ― INTS0 INTA0 INTTX0 INTRX0 INTNAK0 INTSTOP0 ― ― CLRS0 CLRA0 CLRTX0 CLRRX0 CLRNAK0 CLRSTOP0 IRQ1 00H ― ― INTS1 INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 ― ― CLRS1 CLRA1 CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1 IRQ2 00H ― ― ― ― INTADC INTV INTE1 INTMR ― ― ― ― CLRADC CLRV CLRE1 CLRMR Selection of Edge Triggered for INTV, INTE0 & 1 Interrupts TRIGGER FFH ― ― ― ― ― INTVR INTE1R INTE0R Control Registers for Clearing Watch Dog Timer CLR WDT ― 0 1 0 10 1 0 1 Control Register for DDC1/2B+ of Channel 0 CH0ADDR A0H ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ― CH0TXDAT 00H TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 CH0RXDAT 00H RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 CH0CON E0H ENDDC MD1/ 2 ― START STOP ― TXACK ― ― ― SRW START STOP ― ― ― CH0CLK FFH MODE MRW RSTART ― ― DDC2BR2 DDC2BR1 DDC2BR0 Control Register for DDC1/2B+ of Channel 1 CH1ADDR A0H ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ― CH1TXDAT 00H TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 CH1RXDAT 00H RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 R/W R W R RW RW RW RW R W R W R W R/W W W W R W R W W W R 11 11 Page

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