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PDF SCC68681 Data sheet ( Hoja de datos )
| Número de pieza | SCC68681 | |
| Descripción | Dual asynchronous receiver/transmitter | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
SCC68681
Dual asynchronous receiver/transmitter
(DUART)
Product data
2004 Apr 06
Philips
Semiconductors
1 page  
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC68681
BLOCK DIAGRAM
D0–D7
8
BUS BUFFER
R/WN
DTACKN
CSN
A1–A4
RESETN
4
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTRN
IACKN
INTERRUPT CONTROL
IMR
ISR
IVR
X1/CLK
X2
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL OSC
CSRA
CSRB
ACR
CTLUR
CTLR
CHANNEL A
TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
RECEIVE
HOLDING REG (3)
RECEIVE
SHIFT REGISTER
MR1, 2
CRA
SRA
CHANNEL B
(AS ABOVE)
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
IPCR
ACR
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPCR
OPR
Figure 2. Block Diagram
TxDA
RxDA
TxDB
RxDB
6 IP0-IP5
8
OP0-OP7
VCC
GND
SD00108
2004 Apr 06
5
5 Page 
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC68681
MR1A – Channel A Mode Register 1
MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRA. After reading or writing MR1A, the pointer will point
to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Control
This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
However, OPR[0] is not reset and RTSAN will be asserted again
when an empty FIFO position is available. This feature can be used
for flow control to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input of the transmitting
device.
MR1A[6] – Channel A Receiver Interrupt Select
This bit selects either the Channel A receiver ready status (RxRDY)
or the Channel A FIFO full status (FFULL) to be used for CPU
interrupts. It also causes the selected bit to be output on OP4 if it is
programmed as an interrupt output via the OPCR.
MR1A[5] – Channel A Error Mode Select
This bit select the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
MR1A[4:3| – Channel A Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it selects
the polarity of the A/D bit.
MR1A[1:0] – Channel A Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2A – Channel A Mode Register 2
MR2A is accessed when the Channel A MR pointer points to MR2,
which occurs after any access to MR1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6] – Channel A Mode Select
Each channel of the DUART can operate in one of four modes.
MR2A[7:6] = 00 is the normal mode, with the transmitter and
receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically
re-transmits the received data. The following conditions are true
while in automatic echo mode:
1. Received data is re-clocked and re-transmitted on the TxDA
output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter need not be
enabled.
4. The Channel A TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for
transmission, i.e. transmitted parity bit is as received.
6. Character framing is checked, but the stop bits are retransmitted
as received.
7. A received break is echoed as received until the next valid start
bit is detected.
8. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
Two diagnostic modes can also be configured. MR2A[7:6] = 10
selects local loopback mode. In this mode:
1. The transmitter output is internally connected to the receiver
input.
2. The transmit clock is used for the receiver.
3. The TxDA output is held HIGH.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the receiver need not be
enabled.
6. CPU to transmitter and receiver communications continue
normally.
The second diagnostic mode is the remote loopback mode, selected
by MR2A[7:6] = 11. In this mode:
1. Received data is re-clocked and re-transmitted on the TxDA
output.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status
conditions are inactive.
4. The received parity is not checked and is not regenerated for
transmission, i.e., transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked, and the stop bits are
retransmitted as received.
7. A received break is echoed as received until the next valid start
bit is detected.
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes: if the
de-selection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop has been re-transmitted.
MR2A[5] – Channel A Transmitter Request-to-Send Control
CAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
2004 Apr 06
11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet SCC68681.PDF ] | |
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