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PDF SCC68692 Data sheet ( Hoja de datos )
| Número de pieza | SCC68692 | |
| Descripción | Dual asynchronous receiver/transmitter DUART | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
SCC68692
Dual asynchronous receiver/transmitter
(DUART)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
Philips
Semiconductors
1 page  
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCC68692
PIN DESCRIPTION
SYMBOL
D0–D7
CSN
R/WN
A1–A4
RESETN
DTACKN
INTRN
IACKN
X1/CLK
X2
RxDA
RxDB
TxDA
TxDB
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
IP3
IP4
IP5
VCC
GND
PIN NO.
25,16,24,17
23,18,22,19
35
8
1,2,5,6
34
9
21
37
32
33
31
10
30
11
29
12
28
13
27
14
26
15
7
4
36
2
39
38
40
20
TYPE
I/O
I
I
I
I
O
O
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
NAME AND FUNCTION
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are
enabled on D0–D7 as controlled by the R/WN and A1–A4 inputs. When CEN is High, the DUART places
the D0–D7 lines in the 3-State condition.
Read/Write: A High input indicates a read cycle and a low input indicates a write cycle, when a cycle is
initiated by assertion of the CSN input.
Address Inputs: Select the DUART internal registers and ports for read/write operations.
Reset: A Low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex
0F, puts OP0–OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inactive
state, with the TxDA and TxDB outputs in the mark (High) state. Resets Test Mode, sets MR pointer to MR1.
Data Transfer Acknowledge: 3-State active-Low output asserted in write, read, or interrupt cycles to
indicate proper transfer of data between the CPU and the DUART.
Interrupt Request: Active-Low, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
Interrupt Acknowledge: Active-Low input indicating an interrupt acknowledge cycle. In response, the
DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
Crystal 2: Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected
although it is permissible to ground it.
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
Channel B Receive Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback
mode. “Mark” is High, “space” is Low.
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback
mode. ‘Mark’ is High, ‘space’ is Low.
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A
receiver 1X clock output.
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B
transmitter 1X clock output, or Channel B receiver 1X clock output.
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN output.
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYAN output.
Output 7: General purpose output or Channel B open-drain, active-Low, TxRDYBN output.
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal
VCC pull-up device supplying 1 to 4 mA of current.
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal
VCC pull-up device supplying 1 to 4 mA of current.
Input 2: General purpose input or Channel B receiver external clock input (RxCB), or counter/timer
external clock input. When external clock is used by the receiver, the received data is sampled on the
rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 mA of current.
Power Supply: +5V supply input.
Ground
1998 Sep 04
5
5 Page 
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCC68692
only upon receipt of an address character. The CPU compares the
received address to its station address and enables the receiver if it
wishes to receive the subsequent data characters. Upon receipt of
another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted
A/D bit is selected by the CPU by programming bit
MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the
A/D bit position, which identifies the corresponding data bits as data
while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position,
which identifies the corresponding data bits as an address. The
CPU should program the mode register prior to loading the
corresponding data bits into the THR.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems. For example, changing the number of bits per
character while the transmitter is active may cause the transmission
of an incorrect character. In general, the contents of the MR, the
CSR, and the OPCR should only be changed while the receiver(s)
and transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1x by
RESET or by issuing a ‘reset pointer’ command via the
corresponding command register. Any read or write of the mode
register while the pointer is at MR1x, switches the pointer to MR2x.
The pointer then remains at MR2x, so that subsequent accesses are
always to MR2x unless the pointer is reset to MR1x as described
above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved
registers at addresses H‘02’ and H‘0A’ should never be read during
normal operation since they are reserved for internal diagnostics.
PROGRAMMING
The operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
Table 1. Register Addressing
A3 A2 A1 A0
READ (RDN = 0)
WRITE (WRN = 0)
0 0 0 0 Mode Register A (MR1A, MR2A)
Mode Register A (MR1A, MR2A)
0 0 0 1 Status Register A (SRA)
0 0 1 0 BRG Test
Clock Select Register A (CSRA)
Command Register A (CRA)
0 0 1 1 Rx Holding Register A (RHRA)
0 1 0 0 Input Port Change Register (IPCR)
0 1 0 1 Interrupt Status Register (ISR)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
0 1 1 0 Counter/Timer Upper Value (CTU)
0 1 1 1 Counter/Timer Lower Value (CTL)
C/T Upper Preset Value (CRUR)
C/T Lower Preset Value (CTLR)
1 0 0 0 Mode Register B (MR1B, MR2B)
1 0 0 1 Status Register B (SRB)
1 0 1 0 1X/16X Test
Mode Register B (MR1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
1 0 1 1 Rx Holding Register B (RHRB)
1 1 0 0 Interrupt Vector Register (IVR)
Tx Holding Register B (THRB)
Interrupt Vector Register (IVR)
1 1 0 1 Input Ports IP0 to IP6
1 1 1 0 Start Counter Command
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
1 1 1 1 Stop Counter Command
Reset Output Port Bits Command
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
MR1A – Channel A Mode Register 1
MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRA. After reading or writing MR1A, the pointer will
point to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Control
This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
1998 Sep 04
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SCC68692.PDF ] | |
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