|
|
PDF LXT9763 Data sheet ( Hoja de datos )
| Número de pieza | LXT9763 | |
| Descripción | Fast Ethernet 10/100 Hex Teansceiver with Full MII | |
| Fabricantes | Intel | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LXT9763 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
LXT9763
Fast Ethernet 10/100 Hex Transceiver with Full MII
Datasheet
The LXT9763 is a six-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical
layer applications at both 10 and 100 Mbps. The mixed-signal adaptive equalization and clock
recovery with proprietary Optimal Signal Processing (OSP™) architecture improves SNR 3 dB
over ideal analog filters. All six network ports provide a combination twisted-pair (TP) or
pseudo-ECL (PECL) interface for a 10/100BASE-TX or 100BASE-FX connection. The
LXT9763 supports both half- and full-duplex operation at 10 and 100 Mbps.
A fully independent Media Independent Interface (MII) for each port provides maximum
control for switch and multi-port adapter applications.
In addition to an expanded set of MDIO registers, the LXT9763 provides three discrete LED
driver outputs for each port. The LXT9763 requires only a single 3.3V power supply.
Applications
s 100BASE-T, 10/100-TX, or 100BASE-FX
Switches and multi-port NICs.
Product Features
s Six independent IEEE 802.3-compliant
10BASE-T or 100BASE-TX ports with
integrated filters.
s Proprietary Optimal Signal Processing™
(OSP™) architecture improves SNR by 3
dB over ideal analog filters.
s Baseline wander correction for improved
100BASE-TX performance.
s 100BASE-FX fiber-optic capability on all
ports.
s Supports both auto-negotiation and legacy
systems without auto-negotiation
capability.
s JTAG boundary scan.
s Six MII ports for independent PHY port
operation.
s Configurable via MDIO port or external
control pins.
s Maskable interrupts.
s Very low power 3.3V operation
(380 mW per channel, typical).
s 208-pin PQFP (0-70 oC ambient
temperature range).
As of January 15, 2001, this document replaces the Level One document
LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII.
Order Number: 249110-001
January 2001
1 page  
Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
LXT9763 Block Diagram ....................................................................................... 9
LXT9763 Pin Assignments ..................................................................................10
LXT9763 Interfaces ............................................................................................17
Port Address Scheme ........................................................................................19
Management Interface Read Frame Structure ...................................................19
Management Interface Write Frame Structure ...................................................20
Interrupt Logic ....................................................................................................20
Initialization Sequence .......................................................................................22
Hardware Configuration Settings .......................................................................23
Overview of Link Establishment .........................................................................25
MII Data Interface ...............................................................................................26
Loopback Paths ..................................................................................................27
100BASE-X Frame Format ................................................................................28
100BASE-TX Data Path .....................................................................................29
Protocol Sublayers .............................................................................................30
LED Pulse Stretching .........................................................................................36
Power and Ground Supply Connections ............................................................41
Typical Twisted-Pair Interface ............................................................................42
Typical Fiber Interface ........................................................................................43
100BASE-TX Receive Timing (4B Mode) ...........................................................47
100BASE-TX Transmit Timing (4B Mode) .........................................................48
100BASE-TX Receive Timing (5B Mode) ..........................................................49
100BASE-TX Transmit Timing (5B Mode) .........................................................50
100BASE-FX Receive Timing ............................................................................51
100BASE-FX Transmit Timing ...........................................................................52
10BASE-T Receive Timing .................................................................................53
10BASE-T Transmit Timing ................................................................................54
10BASE-T SQE (Heartbeat) Timing ...................................................................54
10BASE-T Jab and Unjab Timing ......................................................................55
Auto Negotiation and Fast Link Pulse Timing ....................................................55
Fast Link Pulse Timing .......................................................................................56
MDIO Write Timing (MDIO Sourced by MAC) ....................................................56
MDIO Read Timing (MDIO Sourced by PHY) ....................................................57
Power-Up Timing ................................................................................................57
RESET And Power-Down Recovery Timing ......................................................58
PHY Identifier Bit Mapping .................................................................................64
LXT9763 Package Specification .........................................................................73
Datasheet
5
5 Page 
Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Table 1. LXT9763 MII Signal Descriptions
Pin#
Symbol
Type1
Signal Description2
Data Interface Pins
79 TXD0_0
82 TXD0_1
83 TXD0_2
84 TXD0_3
Transmit Data - Port 0. 4-bit parallel data to be transmitted from port 0 is clocked in
I synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
60 TXD1_0
61 TXD1_1
62 TXD1_2
63 TXD1_3
Transmit Data - Port 1. 4-bit parallel data to be transmitted from port 1 is clocked in
I synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
42 TXD2_0
43 TXD2_1
44 TXD2_2
45 TXD2_3
Transmit Data - Port 2. 4-bit parallel data to be transmitted from port 2 is clocked in
I synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
24 TXD3_0
25 TXD3_1
26 TXD3_2
27 TXD3_3
Transmit Data - Port 3. 4-bit parallel data to be transmitted from port 3 is clocked in
I synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
6 TXD4_0
7 TXD4_1
8 TXD4_2
9 TXD4_3
Transmit Data - Port 4. 4-bit parallel data to be transmitted from port 4 is clocked in
I synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
196 TXD5_0
197 TXD5_1
198 TXD5_2
199 TXD5_3
Transmit Data - Port 5. 4-bit parallel data to be transmitted from port 5 is clocked in
I synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
77 TX_EN0
59 TX_EN1
41 TX_EN2
23 TX_EN3
5 TX_EN4
195 TX_EN5
I
Transmit Enable - Ports 0 - 5. Active High input enables respective port transmitter.
This signal must be synchronous to the TX_CLK.
75 TX_ER0/TXD0_4
57 TX_ER1/TXD1_4
39 TX_ER2/TXD2_4
21 TX_ER3/TXD3_4
3 TX_ER4/TXD4_4
191 TX_ER5/TXD5_4
Transmit Coding Error - Ports 0 - 5. Valid during 100 Mbps operation only. This
signal must be driven synchronously to TX_CLK. When High, forces the respective
port to transmit Halt (H) code group.
I
Transmit Data - Ports 0 - 5. During symbol mode operation (16.11 = 1), these
signals are re-mapped to provide the fifth data bit (TXDn_4) for their respective ports
(n).
76 TX_CLK0
58 TX_CLK1
40 TX_CLK2
22 TX_CLK3
4 TX_CLK4
194 TX_CLK5
Transmit Clock - Ports 0 - 5. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps
O
operation. The transmit data and control signals must always be synchronized to
TX_CLK by the MAC. The LXT9763 samples these signals on the rising edge of
TX_CLK.
71 RXD0_0
70 RXD0_1
69 RXD0_2
66 RXD0_3
Receive Data - Port 0. Data received at network port 0 is output in 4-bit parallel
O nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the
receive error signals are re-mapped to provide a fifth data bit.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-32) and Y is the bit number (0-15).
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT9763.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LXT9763 | Fast Ethernet 10/100 Hex Teansceiver with Full MII | Intel |
| LXT9763 | Fast Ethernet 10/100 Hex Teansceiver with Full MII |  Level One |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |