PDF EM636165TS Data sheet ( Hoja de datos )

Número de pieza	EM636165TS
Descripción	1M x 16 Synchronous DRAM
Fabricantes	Etron
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No Preview Available ! EtronTech EM636165TS 1M x 16 bit Synchronous DRAM (SDRAM) Advanced (Rev. 5.0, Nov. /2011) Features • Fast access time: 4.5/5.4/5.4ns • Fast clock rate: 200/166/143 MHz • Self refresh mode: standard • Internal pipelined architecture • 512K word x 16-bit x 2-bank • Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function • Individual byte controlled by LDQM and UDQM • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • CKE power down mode • JEDEC standard +3.3V±0.3V power supply • Operating Temperature: TA = 0~70°C • Interface: LVTTL • 50-pin 400 mil plastic TSOP II package -Pb and Halogen Free Overview The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications Table 1. Key Specifications EM636165 tCK3 Clock Cycle time(min.) tRAS Row Active time (min.) tAC3 Access time from CLK (max.) tRC Row Cycle time(min.) Table 2. Ordering Information Part Number Frequency EM636165TS-5G 200MHz EM636165TS-6G 166MHz EM636165TS-7G 143MHz TS: indicates TSOP II package G: indicates Pb and Halogen Free -5/6/7 5/6/7 40/42/42 4.5/5.4/5.4 55/60/63 Type TSOPII TSOPII TSOPII ns ns ns ns Etron Technology, Inc. No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc. reserves the right to change products or specification without notice. 1 page EtronTech EM636165TS DQ0-DQ15 Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are byte-maskable during Reads and Writes. NC - No Connect: These pins should be left unconnected. VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V ) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VDD Supply Power Supply: 3.3V ± 0.3V VSS Supply Ground Rev. 5.0 5 Nov. /2011 5 Page EtronTech EM636165TS CLK COMMAND T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP WRITE A READ B NOP NOP NOP NOP NOP NOP CAS# Latency=2 tCK2, DQ DIN A0 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS# Latency=3 tCK3, DQ DIN A0 don’t care don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 T7 CLK DQM COMMAND WRITE NOP NOP Precharge tRP NOP NOP Activate NOP ADDRESS DQ Bank Col n DIN n tWR DIN N+1 Bank (s) ROW Don’t Care Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2. Figure 13. Write to Precharge 7 Write and AutoPrecharge command (refer to the following figure) (RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP (min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CLK COMMAND Bank A Activate NOP NOP WRITE A Auto Precharge NOP NOP tDAL NOP NOP NOP DQ DIN A0 DIN A1 tDAL=tWR+tRP Begin AutoPrecharge Bank can be reactivated at completion of tDAL Figure 14. Burst Write with Auto-Precharge (Burst Length = 2) Bank A Activate Rev. 5.0 11 Nov. /2011 11 Page

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