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PDF ICX406AQF Data sheet ( Hoja de datos )
| Número de pieza | ICX406AQF | |
| Descripción | Diagonal 8.98mm (Type 1/1.8) Frame Readout CCD Image Sensor | |
| Fabricantes | Sony | |
| Logotipo |  |
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ICX406AQF
Diagonal 8.98mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras
Description
The ICX406AQF is a diagonal 8.98mm (Type 1/1.8)
interline CCD solid-state image sensor with a square
pixel array and 3.98M effective pixels. Frame readout
allows all pixels' signals to be output independently
within approximately 1/3.33 second.
Also, number of vertical pixels decimation allows
output of 30 frames per second in high frame rate
readout mode.
This chip features an electronic shutter with
variable charge-storage time.
R, G, B primary color mosaic filters are used as the
color filters, and at the same time high sensitivity and
low dark current are achieved through the adoption
of Super HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, etc.
20 pin SOP (Plastic)
Features
• Supprots frame readout
• High horizontal and vertical resolution
Pin 1
• Supports high frame rate readout mode: 30 frames/s, 25 frames/s,
AF1 mode: 60 frames/s, 50 frames/s,
2
AF2 mode: 120 frames/s, 100 frames/s
• Square pixel
• Horizontal drive frequency: 18MHz
V
• No voltage adjustments (reset gate and substrate bias are not adjusted.)
• R, G, B primary color mosaic filters on chip
• High sensitivity, low dark current
• Continuous variable-speed shutter
• Excellent anti-blooming characteristics
16
Pin 11
H
12
56
• Exit pupil distance recommended range –20 to –100mm
• 20-pin high-precision plastic package
Optical black position
(Top View)
Device Structure
• Interline CCD image sensor
• Total number of pixels:
2384 (H) × 1734 (V) approx. 4.13M pixels
• Number of effective pixels: 2312 (H) × 1720 (V) approx. 3.98M pixels
• Number of active pixels: 2308 (H) × 1712 (V) approx. 3.95M pixels diagonal 8.980mm
• Number of recommended recording pixels:
2272 (H) × 1740 (V) approx. 3.87M pixels diagonal 8.875mm aspect ratio 4:3
• Chip size:
• Unit cell size:
8.10mm (H) × 6.64mm (V)
3.125µm (H) × 3.125µm (V)
• Optical black:
Horizontal (H) direction: Front 16 pixels, rear 56 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
• Number of dummy bits: Horizontal 28
Vertical 1 (even fields only)
• Substrate material:
Silicon
∗ Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (Hole-
Accumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony
Corporation.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01331-PS
1 page  
ICX406AQF
Clock Equivalent Circuit Constants
Item
Capacitance between vertical transfer clock
and GND
Capacitance between vertical transfer
clocks
Capacitance between horizontal transfer
clock and GND
Symbol
CφV1A, CφV3A
CφV1B, CφV3B
CφV2, CφV4
CφV1A2, CφV3A4
CφV1B2, CφV3B4
CφV23A, CφV41A
CφV23B, CφV41B
CφV1A3A
CφV1B3B
CφV1A3B, CφV1B3A
CφV24
CφV1A1B, CφV3A3B
CφH1, CφH2
Capacitance between horizontal transfer
clocks
CφHH
Capacitance between reset gate clock and
GND
CφRG
Capacitance between substrate clock and
GND
CφSUB
Vertical transfer clock series resistor
R1A, R1B, R2,
R3A, R3B, R4
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
RGND
RφH
Min.
Typ.
1200
4700
3300
470
560
150
220
39
220
56
82
68
36
91
8
1000
62
18
15
Max.
Unit Remarks
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Vφ2
Vφ1A
CφV24
CφV1A2
R1A
R2
CφV1A3A
CφV23B
CφV23A
R3A
Vφ3A
CφV1B2
CφV1A
CφV1A1B
CφV1B3A
CφV1B
CφV41A
CφV2
CφV3A
CφV3A3B
CφV1A3B
CφV3B
R1B
Vφ1B
CφV4
CφV41B
RGND
CφV1B3B
CφV3A4
CφV3B4
R3B
Vφ3B
R4
RφH
Hφ1
RφH
Hφ1
CφHH
CφH1
RφH
Hφ2
RφH
Hφ2
CφH2
Vφ4
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
–5–
5 Page 
ICX406AQF
Readout modes
1. Readout modes list
Mode name
Frame readout mode
NTSC mode
PAL mode
High frame rate readout
mode
NTSC mode
PAL mode
AF1 mode
NTSC mode
PAL mode
AF2 mode
NTSC mode
PAL mode
Frame rate
3.33 frame/s
3.57 frame/s
30 frame/s
25 frame/s
60 frame/s
50 frame/s
120 frame/s
100 frame/s
2. Frame readout mode, high frame rate readout mode
Frame readout mode
1st field
2nd field
Number of effective output lines
1720 (Odd 860, Even 860)
1720 (Odd 860, Even 860)
215
215
97
119
35
46
High frame rate readout mode
VOUT
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
VOUT
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
VOUT
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
Note) Blacked out portions in the diagram indicate pixels which are not read out.
1. Frame readout mode
In this mode, all pixel signals are divided into two fields and output.
All pixel signals are read out independently, making this mode suitable for high resolution image capturing.
2. High frame rate readout mode
Output is performed at 30 frames per second by reading out 4 pixels for every 16 vertical pixels and adding
2 pixels in the horizontal CCD.
The number of output lines is 215 lines.
This readout mode emphasizes processing speed over vertical resolution.
– 11 –
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet ICX406AQF.PDF ] | |
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