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PDF SCN68681 Data sheet ( Hoja de datos )
| Número de pieza | SCN68681 | |
| Descripción | Dual asynchronous receiver/transmitter DUART | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
SCN68681
Dual asynchronous receiver/transmitter
(DUART)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
Philips
Semiconductors
1 page  
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCN68681
PIN DESCRIPTION
SYMBOL TYPE
NAME AND FUNCTION
D0-D7
CSN
I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART and the
CPU. D0 is the least significant bit.
I Chip Select: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on
D0-D7 as controlled by the R/WN, RDN and A1-A4 inputs. When High, places the D0-D7 lines in the 3-State condition.
R/WN
A1-A4
I Read/Write: A High input indicates a read cycle and a Low input indicates a write cycle, when a cycle is initiated by
assertion of the CSN input.
I Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESETN
I
Reset: A Low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex 0F, puts
OP0-OP7 in the High state, stops the counter/timer, and puts Channel A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Clears Test modes, sets MR pointer to MR1.
DTACKN O
Data Transfer Acknowledge: Three-state active Low output asserted in write, read, or interrupt cycles to indicate
proper transfer of data between the CPU and the DUART.
INTRN
O Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.
IACKN
I Interrupt Acknowledge: Active-Low input indicating an interrupt acknowledge cycle. In response, the DUART will
place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
X1/CLK I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally
3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
X2 I Crystal 2: Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected although
it is permissible to ground it.
RxDA
RxDB
I Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
I Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.
TxDA
O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
“mark” condition when the transmitter is disabled, idle or when operating in local loopback mode. “Mark” is High,
“space” is Low.
TxDB
O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is High,
‘space’ is Low.
OP0
OP1
OP2
O Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated
automatically on receive or transmit.
O Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated
automatically on receive or transmit.
O Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock
output.
OP3
OP4
OP5
O Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter 1X clock
output, or Channel B receiver 1X clock output.
O Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA output.
O Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB output.
OP6
O Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output.
OP7
O Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYB output.
IP0 I Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal VCC
pull-up device supplying 1 to 4 mA of current.
IP1 I Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal VCC
pull-up device supplying 1 to 4 mA of current.
IP2 I Input 2: General purpose input, or Channel B receiver external clock input (RxCB), or counter/timer external clock
input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
Pin has an internal VCC pull-up device supplying 1 to 4 mA of current.
IP3 I Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is
used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC
pull-up device supplying 1 to 4 mA of current.
IP4 I Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used
by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device
supplying 1 to 4 mA of current.
IP5 I Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is
used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC
pull-up device supplying 1 to 4 mA of current.
VCC
GND
I Power Supply: +5V supply input.
I Ground:
1998 Sep 04
5
5 Page 
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCN68681
Table 2. Register Bit Formats
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MR1A
MR1B
RxRTS
CONTROL
0 = No
1 = Yes
RxINT
SELECT
0 = RxRDY
1 = FFULL
ERROR
MODE*
0 = Char
1 = Block
PARITY MODE
00 = With Parity
01 = Force Parity
10 = No Parity
11 = Multidrop Mode
PARITY
TYPE
0 = Even
1 = Odd
BITS PER
CHARACTER
00 = 5
01 = 6
10 = 7
11 = 8
NOTE:
*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
BIT 7
BIT 6
BIT 5
BIT 4
MR2A
MR2B
CHANNEL MODE
00 = Normal
01 = Auto-Echo
10 = Local loop
11 = Remote loop
TxRTS
CONTROL
0 = No
1 = Yes
CTS
ENABLE Tx
0 = No
1 = Yes
NOTE:
*Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char.
BIT 3
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
BIT 2
BIT 1
STOP BIT LENGTH*
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
8 = 1.563
9 = 1.625
A = 1.688
B = 1.750
BIT 0
C = 1.813
D = 1.875
E = 1.938
F = 2.000
CSRA
CSRB
BIT 7
BIT 6
BIT 5
RECEIVER CLOCK SELECT
See Text
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TRANSMITTER CLOCK SELECT
See Text
NOTE:
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CRA
CRB
Not used –
should be 0
MISCELLANEOUS COMMANDS
See Text
DISABLE Tx
0 = No
1 = Yes
ENABLE Tx
0 = No
1 = Yes
DISABLE Rx
0 = No
1 = Yes
ENABLE Rx
0 = No
1 = Yes
NOTE:
*Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter cannot
be loaded.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SRA
SRB
RECEIVED
BREAK*
0 = No
1 = Yes
FRAMING
ERROR*
0 = No
1 = Yes
PARITY
ERROR*
0 = No
1 = Yes
OVERRUN
ERROR
0 = No
1 = Yes
TxEMT
0 = No
1 = Yes
TxRDY
0 = No
1 = Yes
FFULL
0 = No
1 = Yes
RxRDY
0 = No
1 = Yes
NOTE:
*These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the
top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are discarded when
the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error reset
command (command 4x) or a receiver reset.
OPCR
BIT 7
OP7
0 = OPR[7]
1 = TxRDYB
BIT 6
OP6
0 = OPR[6]
1 = TxRDYA
BIT 5
OP5
0 = OPR[5]
1 = RxRDY/
FFULLB
BIT 4
OP4
0 = OPR[4]
1 = RxRDY/
FFULLA
BIT 3
BIT 2
OP3
00 = OPR[3]
01 = C/T OUTPUT
10 = TxCB(1x)
11 = RxCB(1x)
BIT 1
BIT 0
OP2
00 = OPR[2]
01 = TxCA(16x)
10 = TxCA(1x)
11 = RxCA(1x)
OPR
BIT 7
BIT 6
BIT 5
BIT 4
OPR bit 0 1 0 1 0 1 0 1
OP pin 1 0 1 0 1 0 1 0
NOTE:
The level at the OP pin is the inverse of the bit in the OPR register.
BIT 3
01
10
BIT 2
01
10
BIT 1
01
10
BIT 0
01
10
1998 Sep 04
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet SCN68681.PDF ] | |
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