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ACS8510REV fiches techniques PDF

Semtech - Synchronous Equipment Timing Source for SONET or SDH Network Elements

Numéro de référence ACS8510REV
Description Synchronous Equipment Timing Source for SONET or SDH Network Elements
Fabricant Semtech 
Logo Semtech 





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ACS8510REV fiche technique
ADVANCED COMMUNICATIONS
ACS8510 Rev2.1 SETS
Synchronous Equipment Timing Source
for SONET or SDH Network Elements
FINAL
Description
Features
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Net-
work Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchro-
nization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
The device supports Free-run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
Rev2.1 adds choice of edge alignment for 8kHz
input, as well as a low jitter n x E1/DS1 output
mode. Other minor changes are made, with all
described in Appendix A.
Block Diagram
Figure 1. Simple Block Diagram
•Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
•Meets AT&T, ITU-T, ETSI and Telcordia
specifications
•Accepts 14 individual input reference clocks
•Generates 11 output clocks
•Supports Free-run, Locked and Holdover
modes of operation
•Robust input clock source quality monitoring on
all inputs
•Automatic ‘hit-less’ source switchover on loss
of input
•Phase build out for output clock phase
continuity during input switchover and mode
transitions
•Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EPROM
•Programmable wander and jitter tracking
attenuation 0.1 Hz to 20 Hz
•Support for Master/Slave device configuration
alignment and hot/standby redundancy
•IEEE 1149.1 JTAG Boundary Scan
•Single +3.3 V operation, +5 V I/O compatible
•Operating temperature (ambient) -40°C to
+85°C
•Available in 100 pin LQFP package
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
2 x AMI
10 x TTL
2 x PECL/LVDS
Programmable;
64/8kHz
2kHz
4kHz
N x 8kHz
1.544/2.048MHz
6.48MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
TCK
TDI
TMS
TRST
TDO
Input
Ports
14xSEC
TOUT4
selector
Monitors
Divider
Digital
PFD Loop
Filter
DPLL/Freq. Synthesis
DTO
MFrSync
IEEE
1149.1
JTAG
TOUT0
selector
Divider
Digital
PFD Loop DTO
Filter
DPLL/Freq. Synthesis
Chip Clock
Generator
Priority
Table
Register
Set
Microprocessor
Port
APLL
Frequency
Dividers
Output
Ports
9xSEC
FrSync
MFrSync
1 x AMI
6 x TTL
2 x PECL/LVDS
Programmable:
64/8kHz
1.544/2.048MHz
3.088/4.096MHz
6.176/8.182MHz
12.352/16.384MHz
6.48MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
311.04MHz
2kHz MFrSync
8kHz FrSync
TCXO (*OCXO)
Revision 2.00/September 2003 Semtech Corp.
www.semtech.com

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