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PDF HD643304x Data sheet ( Hoja de datos )
| Número de pieza | HD643304x | |
| Descripción | Hitachi Single-Chip Microcomputer | |
| Fabricantes | Hitachi | |
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Hitachi Single-Chip Microcomputer
H8/3048 Series
H8/3048
HD64F3048, HD6473048, HD6433048
H8/3047
HD6433047
H8/3045
HD6433045
H8/3044
HD6433044
Hardware Manual
ADE-602-073B
1 page  
5.1.3 Pin Configuration............................................................................................ 83
5.1.4 Register Configuration.................................................................................... 83
5.2 Register Descriptions...................................................................................................... 84
5.2.1 System Control Register (SYSCR)................................................................. 84
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 85
5.2.3 IRQ Status Register (ISR) .............................................................................. 92
5.2.4 IRQ Enable Register (IER) ............................................................................. 93
5.2.5 IRQ Sense Control Register (ISCR) ............................................................... 94
5.3 Interrupt Sources............................................................................................................. 95
5.3.1 External Interrupts .......................................................................................... 95
5.3.2 Internal Interrupts ........................................................................................... 96
5.3.3 Interrupt Vector Table ..................................................................................... 96
5.4 Interrupt Operation ......................................................................................................... 100
5.4.1 Interrupt Handling Process ............................................................................. 100
5.4.2 Interrupt Sequence .......................................................................................... 105
5.4.3 Interrupt Response Time................................................................................. 106
5.5 Usage Notes .................................................................................................................... 107
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ................ 107
5.5.2 Instructions that Inhibit Interrupts .................................................................. 108
5.5.3 Interrupts during EEPMOV Instruction Execution......................................... 108
5.5.4 Notes on External Interrup to during Use....................................................... 108
Section 6 Bus Controller............................................................................................ 111
6.1 Overview......................................................................................................................... 111
6.1.1 Features........................................................................................................... 111
6.1.2 Block Diagram................................................................................................ 112
6.1.3 Input/Output Pins............................................................................................ 113
6.1.4 Register Configuration.................................................................................... 113
6.2 Register Descriptions...................................................................................................... 114
6.2.1 Bus Width Control Register (ABWCR) ......................................................... 114
6.2.2 Access State Control Register (ASTCR) ........................................................ 115
6.2.3 Wait Control Register (WCR)......................................................................... 116
6.2.4 Wait State Controller Enable Register (WCER)............................................. 117
6.2.5 Bus Release Control Register (BRCR)........................................................... 118
6.2.6 Chip Select Control Register (CSCR) ............................................................ 119
6.3 Operation ........................................................................................................................ 121
6.3.1 Area Division.................................................................................................. 121
6.3.2 Chip Select Signals ......................................................................................... 123
6.3.3 Data Bus.......................................................................................................... 124
6.3.4 Bus Control Signal Timing ............................................................................. 125
6.3.5 Wait Modes ..................................................................................................... 133
5 Page 
13.2.6 Serial Control Register (SCR) ........................................................................ 447
13.2.7 Serial Status Register (SSR) ........................................................................... 451
13.2.8 Bit Rate Register (BRR) ................................................................................. 455
13.3 Operation ........................................................................................................................ 464
13.3.1 Overview......................................................................................................... 464
13.3.2 Operation in Asynchronous Mode.................................................................. 466
13.3.3 Multiprocessor Communication ..................................................................... 475
13.3.4 Synchronous Operation .................................................................................. 482
13.4 SCI Interrupts.................................................................................................................. 491
13.5 Usage Notes .................................................................................................................... 492
Section 14 Smart Card Interface ................................................................................ 497
14.1 Overview......................................................................................................................... 497
14.1.1 Features........................................................................................................... 497
14.1.2 Block Diagram................................................................................................ 498
14.1.3 Input/Output Pins............................................................................................ 499
14.1.4 Register Configuration.................................................................................... 499
14.2 Register Descriptions...................................................................................................... 500
14.2.1 Smart Card Mode Register (SCMR)............................................................... 500
14.2.2 Serial Status Register (SSR) ........................................................................... 501
14.2.3 Serial Mode Register (SMR) .......................................................................... 503
14.2.4 Serial Control Register (SCR) ........................................................................ 504
14.3 Operation ........................................................................................................................ 505
14.3.1 Overview......................................................................................................... 505
14.3.2 Pin Connections .............................................................................................. 505
14.3.3 Data Format .................................................................................................... 506
14.3.4 Register Settings ............................................................................................. 508
14.3.5 Clock............................................................................................................... 510
14.3.6 Transmitting and Receiving Data ................................................................... 512
14.4 Usage Notes .................................................................................................................... 519
Section 15 A/D Converter............................................................................................ 523
15.1 Overview......................................................................................................................... 523
15.1.1 Features........................................................................................................... 523
15.1.2 Block Diagram................................................................................................ 524
15.1.3 Input Pins ........................................................................................................ 525
15.1.4 Register Configuration.................................................................................... 526
15.2 Register Descriptions...................................................................................................... 527
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ........................................ 527
15.2.2 A/D Control/Status Register (ADCSR) .......................................................... 528
15.2.3 A/D Control Register (ADCR) ....................................................................... 531
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD643304x.PDF ] | |
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