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PDF AD1941 Data sheet ( Hoja de datos )
| Número de pieza | AD1941 | |
| Descripción | 28 Bit Audio Processor | |
| Fabricantes | Analog | |
| Logotipo |  |
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Preliminary Technical Data
FEATURES
16-channel digital audio processor
Accepts sample rates up to 192 kHz
28-bit × 28-bit multiplier with full 56-bit accumulator
Fully-programmable program RAM for custom
program download
Parameter RAM allows complete control of 1,024 parameters
Control port features safeload for transparent parameter
updates and complete mode and memory transfer control
Target/slew RAM for click-free volume control and dynamic
parameter updates
Double precision mode for full 56-bit processing
PLL for generating MCLK from 64 × fS, 256 × fS, 384 × fS, or
512 × fS clocks
Hardware-accelerated DSP core
21 kB (6,144 words) data memory for up to 128 ms of audio
delay at fs = 48 kHz
Flexible serial data port with I2S compatible, left-justified,
and right-justified serial port modes
8- and 16-channel TDM input/output modes
On-chip voltage regulator for compatibility with 3.3 V and
5 V systems
Programmable low power mode
Fast start-up and boot time from power on or reset
48-lead LQFP plastic package
GENERAL DESCRIPTION
The AD1941 is a complete 28-bit, single-chip, multichannel
audio DSP for equalization, multiband dynamics processing,
delay compensation, speaker compensation, and image
enhancement. These algorithms can be used to compensate for
the real-world limitations of speakers, amplifiers, and listening
environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1941 is comparable to that
found in high end studio equipment. Most of the processing is
done in full, 56-bit double-precision mode, resulting in very
good low level signal performance and the absence of limit
cycles or idle tones. The dynamics processor uses a sophisti-
cated, multiple-breakpoint algorithm often found in high end
broadcast compressors.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SigmaDSPTM Multichannel
28-Bit Audio Processor
AD1941
APPLICATIONS
Automotive sound systems
Digital televisions
Home theater systems (Dolby Digital/DTS postprocessor)
Multichannel audio systems
Mini-component stereos
Multimedia audio
Digital speaker crossover
Musical instruments
In-seat sound systems (aircrafts/motor coaches)
FUNCTIONAL BLOCK DIAGRAM
4
VOLTAGE
REGULATOR
2
SERIAL DATA/
TDM INPUTS
MASTER
CLOCK
INPUT
PLL
4
SPI I/O
SERIAL
CONTROL
INTERFACE
AD1940
28 × 28
DSP CORE
2
2
DATA FORMAT:
5.23 (SINGLE
PRECISION)
10.46 (DOUBLE
PRECISION)
RAM ROM
SERIAL
DATA/
TDM
OUTPUTS
Figure 1.
The AD1941 is a fully-programmable DSP. Easy to use software
allows the user to graphically configure a custom signal
processing flow using blocks such as biquad filters, dynamics
processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.
The AD1941’s digital input and output ports allow a glueless
connection to ADCs and DACs by multiple, 2-channel serial
data streams or TDM data streams. When in TDM mode, the
AD1941 can input 8 or 16 channels of serial data, and can
output either 8 or 16 channels of serial data. The input and
output port configurations can be individually set. The AD1941
is controlled on a 2-wire I2C bus.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
Min
VDD to DGND
–0.3
PLL_ VDD to PGND
–0.3
OD VDD to DGND
–0.3
INVDD to DGND
ODVDD
Digital Inputs
DGND – 0.3
Maximum Junction Temperature
Storage Temperature Range
–65
Soldering (10 sec)
Max
+3.0
+3.0
+6.0
+6.0
INVDD + 0.3
135
+150
300
Unit
V
V
V
V
V
°C
°C
°C
AD1941
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 9. Package Characteristics
Parameter
θJA Thermal Resistance (Junction-to-Ambient)
θJC Thermal Resistance (Junction-to-Case)
Min Typ
Max Unit
72 °C/W
19.5 °C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE | Page 5 of 32
5 Page 
Preliminary Technical Data
PIN FUNCTIONS
Table 10 shows the AD1941’s pin numbers, names, and
functions. Input pins have a logic threshold compatible with
TTL input levels and may be used in systems with 3.3 V or
5 V logic.
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
Serial Data/TDM Inputs. The serial format is selected by writing
to Bits 2:0 of the serial input port control register. SDATA_IN2
and SDATA_IN3 are dual-function pins that can be set to a
variety of standard 2-channel formats or to TDM mode. Two of
these four pins (SDATA_IN2 and SDATA_IN3) can be used as
TDM inputs in either dual-wire 8-channel mode or single-wire
16-channel mode (TDM_O0 only). In dual-wire 8-channel
mode, Channels 0-7 will be input on SDATA_IN3 and
Channels 8-15 on SDATA_IN2. In single-wire 16-channel
mode, Channels 0-15 will be input on SDATA_IN2. See the
Serial Data Input/Output Ports section for further explanation.
LRCLK_IN
BCLK_IN
Left/Right and Bit Clocks for Timing the Input Data. These
input clocks are associated with the SDATA_IN0-3 signals. The
input port is always in a slave configuration. These pins also
function as frame sync and bit clock for the input TDM stream.
SDATA_OUT0/TDM_O0
SDATA_OUT1
SDATA_OUT2,
SDATA_OUT3
SDATA_OUT4/TDM_O1
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7/DCSOUT
Serial Data/TDM/Data Capture Outputs. These pins are used
for serial digital outputs. For non-TDM systems, these eight
pins can output 16 channels of digital audio, using a variety of
standard two-channel formats. They are grouped into two
groups of four pins (0-3 and 4-7); each group can be indepen-
dently set to any of the available serial modes, allowing the
AD1941 to simultaneously communicate with two external
devices with different serial formats. Two of these eight pins
(SDATA_OUT0 and SDATA_OUT4) can be used as TDM
outputs in either dual-wire 8-channel mode or single-wire
16-channel mode (TDM_OUT0 only). In dual-wire 8-channel
mode, Channels 0-7 will be output on SDATA_OUT0 and
Channels 8-15 on SDATA_OUT4. See the Serial Data
Input/Output Ports section for further explanation.
SDATA_OUT7 can also be used as a data capture output, as
described in the Data Capture Registers section.
AD1941
LRCLK_OUT0
BCLK_OUT0
Output Clocks. This clock pair is used for outputs
SDATA_OUT0–3. In slave mode, these clocks are inputs
to the AD1941. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
LRCLK_OUT1
BCLK_OUT1
Output Clocks. This clock pair is used for outputs
SDATA_OUT4–7. In slave mode, these clocks are inputs
to the AD1941. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
MCLK
Master Clock Input. The AD1941 uses a PLL to generate the
appropriate internal clock for the DSP core. An in-depth
description of using the PLL is found in the Setting Master
Clock/PLL Mode section.
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL Mode Control Pins. The functionality of these pins is
described in the Setting Master Clock/PLL Mode section.
SCL
I2C Clock. This pin is always an input because the AD1941
cannot act as a master on the I2C bus. The line connected to this
pin should have a 2 kΩ pull-up resistor on it.
SDA
I2C Serial Data. The data line is bidirectional. The line
connected to this pin should have a 2 kΩ pull-up resistor on it.
I2C_FILT_ENB
I2C Spike Filter Enable/Disable. This enables (active low) the I2C
spike filter, which is used to prevent noise or glitches on the I2C
bus, from improperly affecting the AD1941.
ADR_SEL
Address Select. This pin selects the address for the AD1941’s
communication with the control port. This allows two AD1941s
to be used with a single CLATCH signal.
RESETB
Active-Low Reset Signal. After RESETB goes high, the AD1941
goes through an initialization sequence where the program and
parameter RAMs are initialized with the contents of the on-
board boot ROMs. All registers are set to 0, and the data RAMs
are also set to 0. The initialization is complete after
8,192 internal MCLK cycles (referenced to the rising edge of
RESETB), which corresponds to 1,366 external MCLK cycles if
the part is in 256 × fS mode. New values should not be written to
the control port until the initialization is complete.
Rev. PrE | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD1941.PDF ] | |
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