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UPD4516161D fiches techniques PDF

Elpida - 16M Bit Synchronous DRAM

Numéro de référence UPD4516161D
Description 16M Bit Synchronous DRAM
Fabricant Elpida 
Logo Elpida 





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UPD4516161D fiche technique
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4516161D
16M-bit Synchronous DRAM
2-banks, LVTTL
Description
The µPD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as
524,288 words × 16 bits × 2 banks respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
This product is packaged in 50-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Dual internal banks controlled by A11
Byte control by LDQM and UDQM
Programmable Wrap sequence: Sequential / Interleave
Programmable burst length: 1, 2, 4, 8 and full page
/CAS latency: 3
CBR (Auto) refresh and self refresh
• ×16 organization
Single 3.3 V ± 0.3 V power supply
LVTTL compatible
2,048 refresh cycles / 32 ms
Burst termination by Burst stop command and Precharge command
Ordering Information
Part number
µPD4516161DG5-A70-9NF
µPD4516161DG5-A75-9NF
µPD4516161DG5-A80-9NF
µPD4516161DG5-A10-9NF
Organization
(word × bit × bank)
512K × 16 × 2
Clock frequency
MHz (MAX.)
143
133
125
100
Package
50-pin PLASTIC TSOP (II)
(10.16mm(400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0143N10 (Ver.1.0)
(Previous No. M14888EJ2V0DS00)
Date Published May 2001 CP (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

PagesPages 30
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