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PDF HY5W2A6C Data sheet ( Hoja de datos )
| Número de pieza | HY5W2A6C | |
| Descripción | 4 Bank x 2 M x 16 Bit Synchronous DRAM | |
| Fabricantes | Hynix | |
| Logotipo |  |
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HY5W2A6C(L/S)F-F / HY57W2A1620HC(L/S)T-F
HY5W26CF-F / HY57W281620HCT-F
4Banks x 2M x 16bits Synchronous DRAM
Revision History
Revision No.
0.3
0.4
0.9
1.0
1.1
1.2
1.3
History
1. Datasheet separation (Normal & Low Power)
2. Page2 ~ Page23 : Part Number Change
HY5W26CF -> HY5W2A6CF
3. Page2, 24 : Part Number Change
HY57W281620HCT -> HY57W2A1620HCT
4. Page18,19 : DC Characteristics II & III
Some TBDs -> Fixed Values
Note 3 : current -> current values
5. Page24 : Package Information Change
1. Page1 ~ Page23 : Part Number Change
HY5W2A6CFL -> HY5W2A6CLF
Ball Capacitanace value correction
ICC6 Current correction
ICC6 Current correction
1. ICC1,2 Spec Change
2. Added VDDQ 2.5V Spec.
1. Changed IDD6 Value.
2. Changed Temperature range.
Changed Absolute Max Rating
VDD,VDDQ,Vin,Vout from4.6 to 3.6
Draft Date
June 2001
Remark
July 2001
Dec. 2001
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.3 / Dec. 01
1 page  
FUNCTIONAL BLOCK DIAGRAM
HY5W2A6C(L/S)F-F / HY57W2A1620HC(L/S)T -F
HY5W26CF-F / HY57W281620HCT-F
2Mbit x 4banks x 16 I/O Low Power Synchronous DRAM
CLK
CKE
CS
RAS
CAS
WE
U/LDQM
A0
A1
TCSR, PASR
Extended
Mode
Register
Self refresh
logic & timer
Row
Active
Internal Row
Counter
Row
Pre
Decoders
refresh
Column
Active
Column
pre
Decoders
2Mx16 Bank3
2Mx16 Bank2
2Mx16 Bank1
2Mx16 Bank0
Memory
Cell
Array
Column decoders
bank select
Column Add
Counter
Address
Registers
Burst
Counter
A11
BA1
BA0
Mode
Register
CAS Latency
Data Out
Control
DQ0
DQ15
Rev. 1.3 / Dec. 01
5
5 Page 
HY5W2A6C(L/S)F-F / HY57W2A1620HC(L/S)T -F
HY5W26CF-F / HY57W281620HCT-F
CURRENT STATE TRUTH TABLE (Sheet 1 of 3)
Command
Current State
CS RAS CAS WE BA0,BA1 A11-A0
Description
Action
Notes
LL L L
OP Code
Mode Register Set Set the Mode Register
14
LL L H
X
X Auto or Self Refresh Start Auto or Self Refresh
5
LL H L
BA
X Precharge
No Operation
idle
LL
HH
BA Row Add. Bank Activate
Activate the specified bank and
row
L H L L BA Col Add. Write/WriteAP
ILLEGAL
4
A10
L H L H BA
Col Add. Read/ReadAP
ILLEGAL
4
A10
LH H H
X
X No Operation
No Operation
3
HX X X
X
X Device Deselect
No Operation or Power Down
3
LL L L
OP Code
Mode Register Set ILLEGAL
13,14
LL L H
X
X Auto or Self Refresh ILLEGAL
13
LL H L
BA
X Precharge
Precharge
7
LL
HH
BA Row Add. Bank Activate
ILLEGAL
4
Row
L H L L BA Col Add. Write/WriteAP
Active
A10
Start Write : optional
AP(A10=H)
6
L H L H BA Col Add. Read/ReadAP
A10
Start Read : optional
AP(A10=H)
6
LH H H
X
X No Operation
No Operation
HX X X
X
X Device Deselect
No Operation
LL L L
OP Code
Mode Register Set ILLEGAL
13,14
LL L H
X
X Auto or Self Refresh ILLEGAL
13
Read
LL H L
LL H H
LH L L
BA X Precharge
BA Row Add. Bank Activate
BA Col Add. Write/WriteAP
A10
Termination Burst: Start the
Precharge
ILLEGAL
Termination Burst: Start
Write(optional AP)
4
8,9
L H L H BA Col Add. Read/ReadAP
A10
Termination Burst: Start
Read(optional AP)
8
LH H H
X
X No Operation
Continue the Burst
HX X X
X
X Device Deselect
Continue the Burst
LL L L
OP Code
Mode Register Set ILLEGAL
13,14
LL L H
X
X Auto or Self Refresh ILLEGAL
13
LL H L
BA
X Precharge
Termination Burst: Start the
Precharge
10
Write
LL H H
LH L L
BA Row Add. Bank Activate
BA Col Add. Write/WriteAP
A10
ILLEGAL
Termination Burst: Start
Write(optional AP)
4
8
L H L H BA Col Add. Read/ReadAP
A10
Termination Burst: Start
Read(optional AP)
8,9
LH H H
X
X No Operation
Continue the Burst
HX X X
X
X Device Deselect
Continue the Burst
Rev. 1.3 / Dec. 01
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet HY5W2A6C.PDF ] | |
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