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PDF MAX3885ECB Data sheet ( Hoja de datos )
| Número de pieza | MAX3885ECB | |
| Descripción | +3.3V / 2.488Gbps / SDH/SONET 1:16 Deserializer with LVDS Outputs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-4767; Rev 2; 1/99
EVFAOLLULAOTWIOSNDKAITTAMSAHNEUEATL
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
General Description
The MAX3885 deserializer is ideal for converting
2.488Gbps serial data to 16-bit wide, 155Mbps parallel
data in SDH/SONET applications. Operating from a sin-
gle +3.3V supply, this device accepts PECL serial
clock and data inputs, and delivers low-voltage differ-
ential-signal (LVDS) clock and data outputs for interfac-
ing with high-speed digital circuitry. It also provides an
LVDS synchronization input that enables data realign-
ment and reframing. The MAX3885 is available in the
extended temperature range (-40°C to +85°C) in a 64-
pin TQFP package.
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross Connects
Features
o Single +3.3V Supply
o 2.488Gbps Serial to 155Mbps Parallel Conversion
o 660mW Operating Power
o LVDS Data Outputs and Synchronization Inputs
o Self-Biasing PECL Inputs Ease AC Coupling
o Synchronization Inputs for Data Realignment and
Reframing
PART
MAX3885ECB
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
64 TQFP
Pin Configuration appears at end of data sheet.
SERIAL DATA
INPUTS
VCC = +3.3V
MAX3875
DATA
AND
CLOCK
RECOVERY
Typical Operating Circuit
VCC = +3.3V
VCC = +3.3V
VCC
133Ω
133Ω
PD15+
86.6Ω
86.6Ω
SD+
SD-
MAX3885
PD15-
PD0+
100Ω*
•
•
•
VCC = +3.3V
133Ω
86.6Ω
133Ω
SCLK+
SCLK-
86.6Ω
100Ω*
PD0-
PCLK+
100Ω*
PCLK-
SYNC+
SYNC-
GND
OVERHEAD
TERMINATION
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
Detailed Description
The MAX3885 deserializer uses a 16-bit shift register,
16-bit parallel output register, 4-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 2.488Gbps serial data to
16-bit wide, 155Mbps parallel data (Figure 2). The input
SD+
PECL
SD-
SCLK+
SCLK-
PECL
SYNC+
SYNC-
100Ω LVDS
16-BIT
SHIFT
REGISTER
16-BIT
PARALLEL
OUTPUT
REGISTER
MAX3885
4-BIT
COUNTER
LVDS
LVDS
LVDS
LVDS
PD15+
PD15-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
Figure 2. Functional Diagram
shift register continuously clocks incoming data on the
positive transition of the serial clock (SCLK) input sig-
nal. The 4-bit counter generates a parallel-output clock
(PCLK) by dividing the serial-clock frequency by 16.
The PCLK signal clocks the parallel-output register.
During normal operation, the counter divides the SCLK
frequency by 16, causing the output register to latch
every 16 bits of incoming serial data. The synchroniza-
tion inputs (SYNC+, SYNC-) realign and reframe data.
When the SYNC signal is pulsed high for at least four
SCLK cycles, the parallel output data is delayed by one
SCLK cycle. This realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. As a result, the first incoming bit of
data during that PCLK cycle is dropped, shifting the
alignment between PCLK and data by one bit. See
Figure 3 for the timing diagram and Figure 4 for the tim-
ing parameters diagram.
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3885 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. The parallel clock and data LVDS outputs
(PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential
D15 D14 D13
SCLK
SD
SYNC
PCLK
(LSB) PD0
PD1
•
•
•
(MSB) PD15
TRANSMITTED FIRST
D0
D1
D15
D16
D17
D31
D32 D48
D33 D49
ONE BIT HAS SLIPPED
IN THIS TIME SLICE
D47 D64
D65
D66
D80
Figure 3. Timing Diagram
_______________________________________________________________________________________ 5
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| PDF Descargar | [ Datasheet MAX3885ECB.PDF ] | |
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