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PDF MAX3880 Data sheet ( Hoja de datos )
| Número de pieza | MAX3880 | |
| Descripción | +3.3V / 2.488Gbps / SDH/SONET 1:16 Deserializer with Clock Recovery | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-1467; Rev 1; 12/99
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
General Description
The MAX3880 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers low-
voltage differential-signal (LVDS) parallel clock and
data outputs for interfacing with digital circuitry.
The MAX3880 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3880’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor and LVDS synchronization
inputs that enable data realignment and reframing.
The MAX3880 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed
pad) package.
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
Features
o Single +3.3V Supply
o 910mW Operating Power
o Fully Integrated Clock Recovery and Data
Retiming
o Exceeds ANSI, ITU, and Bellcore Specifications
o Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
o 2.488Gbps Serial to 155Mbps Parallel Conversion
o LVDS Data Outputs and Synchronization Inputs
o Tolerates >2000 Consecutive Identical Digits
o Loss-of-Lock Indicator
PART
MAX3880ECB
*Exposed pad
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
64 TQFP-EP*
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
0.01µF
+3.3V
VCC
FIL OUT+
IN+ MAX3866
PRE/POSTAMPLIFIER
OUT-
LOP
TTL
PHADJ+ PHADJ-
VCC
SDI+
SDI-
SLBI-
SLBI+
MAX3880
PD15+
PD15-
100Ω*
PD0+
100Ω*
PD0-
PCLK+
100Ω*
PCLK-
SYNC+
SYSTEM
LOOPBACK
SIS FIL+
FIL-
CF
TTL 1µF
GND
LOL SYNC-
TTL
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
VCC
OVERHEAD
TERMINATION
________________________________________________________________ Maxim Integrated Products 1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Description
PIN
1, 17, 25, 33,
41, 49, 56,
62, 64
2
3
4, 7, 10, 13,
24, 32, 40,
48, 57
5
NAME
GND
FIL+
FIL-
VCC
PHADJ+
6 PHADJ-
8 SDI+
9 SDI-
11 SLBI+
12 SLBI-
14 SIS
15 SYNC-
16
18
19
20, 22, 26,
28, 30, 34,
36, 38, 42,
44, 46, 50,
52, 54, 58, 60
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
63
SYNC+
PCLK-
PCLK+
PD0- to
PD15-
PD0+ to
PD15+
LOL
EP Exposed Pad
FUNCTION
Ground
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
+3.3V Supply Voltage
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
Positive Serial Data Input. 2.488Gbps data stream.
Negative Serial Data Input. 2.488Gbps data stream.
Positive System Loopback Input. 2.488Gbps data stream.
Negative System Loopback Input. 2.488Gbps data stream.
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
Negative Parallel Clock LVDS Output
Positive Parallel Clock LVDS Output
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pull-up resistor). The
LOL monitor is valid only when a data stream is present on the inputs to the MAX3880.
Ground. This must be soldered to a circuit board for proper thermal performance (see Package
Information).
_______________________________________________________________________________________ 5
5 Page 
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Package Information
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX3880.PDF ] | |
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