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PDF MAX3877EHJ Data sheet ( Hoja de datos )
| Número de pieza | MAX3877EHJ | |
| Descripción | 2.5Gbps / +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-2062; Rev 0; 5/01
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
General Description
The MAX3877/MAX3878 are compact, low-power clock
recovery and data retiming ICs for 2.488Gbps SONET/
SDH applications. The fully integrated phase-locked
loop (PLL) recovers a synchronous clock signal from
the serial NRZ data input, which is retimed by the
recovered clock. An additional 2.488Gbps serial input
is available for system loopback diagnostic testing, or
this input can be connected to a 155MHz reference
clock to maintain a valid clock output in the absence of
data transitions. The MAX3877/MAX3878 provide verti-
cal threshold and phase-adjust control to optimize sys-
tem BER in DWDM applications.
These devices provide both loss-of-lock (LOL) and
loss-of-signal (LOS) monitors. Differential CML outputs
are provided for both clock and data signals on the
MAX3877, and differential PECL outputs are provided
for clock and data signals on the MAX3878.
The MAX3877/MAX3878 are designed for both section-
regenerator and terminal-receiver applications in OC-
48/STM-16 transmission systems. Their jitter performance
exceeds all of the SONET/SDH specifications. These
devices operate from a single +3.0V to +3.6V supply over
a -40°C to +85°C temperature range. Typical power con-
sumption is only 540mW with a +3.3V supply (MAX3878).
They are available in a 32-pin TQFP-EP package with an
exposed pad, as well as in die form.
Applications
Long Haul and Metro Systems with
Optical Amplification
DWDM Transmission Systems
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
Typical Operating Circuit appears at end of data sheet.
Features
o Exceeds ANSI, ITU, and Bellcore SONET/SDH
Specifications
o Adjustable Input Threshold (±180mV)
o 10mVp-p to 1.2Vp-p Differential Input Range
o 540mW Power Dissipation (at +3.3V)
o Fully Integrated Clock Recovery and Data
Retiming
o Optional Holdover Capability (Using External
Reference Clock)
o 0.003UIRMS Clock Jitter Generation
o Tolerates >2000 Consecutive Identical Digits
o Additional 2.488Gbps Input for Diagnostic
Loopback Testing
o Differential PECL or CML Data and Clock Outputs
o Loss-of-Signal Indicator
o Loss-of-Lock Indicator
Ordering Information
PART
TEMP. RANGE PIN-PACKAGE
MAX3877EHJ
-40°C to +85°C 32 TQFP-EP*
MAX3877E/D*** -40°C to +85°C DICE**
MAX3878EHJ
-40°C to +85°C 32 TQFP-EP*
MAX3878E/D*** -40°C to +85°C DICE**
* Exposed pad
** Dice are designed to operate over this range, but are tested
and guaranteed at TA = +25°C only. contact factory for avail-
ability.
*** Future product—contact factory for availability.
Pin Configuration
TOP VIEW
GND 1
THADJ 2
VCC 3
SDI- 4
SDI+ 5
VCC 6
SIS 7
LREF 8
32 31 30 29 28 27 26 25
MAX3877
MAX3878
24 VCC
23 SDO+
22 SDO-
21 VCC
20 VCC
19 SCLKO+
18 SCLKO-
17 VCC
9 10 11 12 13 14 15 16
TQFP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
SDI+
SDI-
(SDI+) -
(SDI-)
5mV MIN
600mV MAX
VID
10mVp-p MIN
1200mVp-p MAX
Figure 1. Input Amplitude
VTH (mV)
+207
+180
-153
0.2
-153
-180
-207
THRESHOLD SETTING ACCURACY
(PART-TO-PART VARIATION OVER PROCESS)
1.1
1.3
2.2
THRESHOLD SETTING STABILITY
(OVER TEMPERATURE OR SUPPLY)
THADJ (V)
Figure 2. Setting the Input Threshold Level
_______________________________________________________________________________________ 5
5 Page 
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
Table 1. Selecting Input Path
LREF = 0
LREF = 1
SIS = 0
SIS = 1
SDI SLBI
(Normal Operation) (System Loopback Mode)
SLBI
(Holdover Mode)
SLBI
(Holdover Mode)
HO(j2πf) (dB)
CF = 1.0µF
fZ = 2.6kHz
CF = 0.1µF
fZ = 26kHz
f (kHz)
1 10 100 1000
Figure 8. Open-Loop Transfer Function
H(j2πf) (dB)
0
-3
CF = 0.1µF
CF = 1.0µF
1 10 100 1000
Figure 9. Closed-Loop Transfer Function
f (kHz)
Design Procedure
Setting the Loop Filter
The MAX3877/MAX3878 are designed for both regenera-
tor and receiver applications. The fully integrated PLL is a
classic second-order feedback system, with a loop band-
width (fL) fixed at 1.4MHz. The external capacitor, CF,
can be adjusted to set the loop damping. Figures 8 and 9
show the open-loop and closed-loop transfer functions.
The PLL zero frequency, fZ, is a function of external
capacitor CF, and can be approximated according to:
fZ
=
1
2π(60)CF
For an overdamped system (fZ / fL < 0.25), the jitter peak-
ing (MP) of a second-order system can be approximated
by:
MP
=
20log 1+
fZ
fL
For example, using CF = 0.1µF results in a jitter peaking
of 0.16dB. Reducing CF below 0.01µF may result in PLL
instability. The recommended value of CF = 1.0µF is to
guarantee a maximum jitter peaking of less than 0.1dB.
CF must be a low-TC, high-quality capacitor of type XR7
or better.
Input Termination
Inputs for the MAX3877/MAX3878 are current-mode logic
(CML) compatible. The inputs all provide internal 50Ω ter-
mination to reduce the required number of external com-
ponents. When interfacing to differential PECL levels, it is
important to attenuate the signal while maintaining a 50Ω
termination (see Figure 10). AC-coupling is also neces-
sary to maintain the input common-mode level.
Output Termination (MAX3877)
The MAX3877 uses current-mode logic (CML) for its high-
speed digital outputs. CML outputs are 50Ω back-termi-
nated, reducing the external component count. Refer to
Figure 11 for the output structure. CML outputs may be
terminated by 50Ω to VCC, or by 100Ω differential imped-
ance.
Output Termination (MAX3878)
The MAX3878 uses positive emitter-coupled logic (PECL)
for its high-speed outputs. PECL outputs are designed to
be terminated by 50Ω to (VCC - 2V). Refer to Applications
Note HFAN 0.1.0, Interfacing Between CML, PECL, and
LVDS, for more information.
______________________________________________________________________________________ 11
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