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PDF MAX3876 Data sheet ( Hoja de datos )
| Número de pieza | MAX3876 | |
| Descripción | 2.5Gbps / Low-Power / #.3V Clock Recovery and Data Retiming IC | |
| Fabricantes | Maxim Integrated | |
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19-1631; Rev 0; 1/00
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
General Description
The MAX3876 is a compact, low-power clock recovery
and data retiming IC for 2.488Gbps SDH/SONET appli-
cations. The fully integrated phase-locked loop (PLL)
recovers a synchronous clock signal from the serial
NRZ data input. The data is retimed by the recovered
clock. Differential CML outputs are provided for both
clock and data signals, and an additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor.
The MAX3876 is designed for both section-regenerator
and terminal-receiver applications in OC-48/STM-16
transmission systems. Its jitter performance exceeds all
of the SONET/SDH specifications.
This device operates from a +3.3V or +5.0V single sup-
ply over a -40°C to +85°C temperature range. Power
consumption is typically only 445mW with a +3.3V sup-
ply. The MAX3876 is available in a 32-pin TQFP pack-
age as well as in die form.
Applications
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
2.488Gbps ATM Receiver
Digital Video Transmission
SDH/SONET Test Equipment
Intrarack/Subrack Interconnects
Features
o Exceeds ANSI, ITU, and Bellcore SONET/SDH
Regenerator Specifications
o 440mW Power Dissipation (at +3.3V)
o Clock Jitter Generation: 3.7mUIRMS
o +3.3V or +5V Single Power Supply
o Fully Integrated Clock Recovery and Data Retiming
o Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
o Tolerates >2500 Consecutive Identical Digits
o Loss-of-Lock Indicator
o Differential CML Data and Clock Outputs
Ordering Information
PART
MAX3876EHJ
MAX3876E/D
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Dice*
*Dice are designed to operate over this range, but are tested
and guaranteed at TA = +25°C only. Contact factory for
availability.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
FILT
0.01µF
PHOTO-
DIODE
IN
VCC
MAX3866
PREAMPLIFIER
0.01µF
OUT+
OUT-
+3.3V
TTL
VCC
SDI+
LOL
SDO+
SDO-
SDI- MAX3876
SLBI+
SLBI-
SIS FIL+
SCLKO+
SCLKO-
FIL-
+3.3V
MAX3831
4:1/1:4
TRANSCEIVER
SYSTEM
LOOPBACK
TTL
1µF
________________________________________________________________ Maxim Integrated Products 1
For free samples and the latest literature: www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
Pin Description (continued)
PIN NAME
FUNCTION
19 SCLKO+ Positive Serial Clock Output, CML, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.
22
SDO-
Negative Data Output, CML, 2.488Gbps
23 SDO+ Positive Data Output, CML, 2.488Gbps
25 LOL Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor)
30 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
31
FIL+
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
SIS FIL+ FIL-
SDI+
SDI-
SLBI+
SLBI-
AMP
MUX
AMP
MAX3876
PHASE AND
FREQUENCY
DETECTOR
LOOP
FILTER
DQ
CK
I
VCO Q
SDO+
CML SDO-
SCLKO+
SCLKO-
CML
LOL
TTL
Figure 3. Functional Diagram
Detailed Description
The MAX3876 consists of a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
and CML output buffer (Figure 3). The PLL consists of
a phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Input Amplifier
Input amplifiers are implemented for both the main data
and system loopback inputs. These amplifiers accept
DC-coupled differential input amplitudes from 50mVp-p
up to 1000mVp-p. With AC-coupling, differential input
signal amplitudes can be increased to a maximum of
1600mVp-p. The bit error rate is better than 1 · 10-10 for
input signals as small as 10mVp-p, though the jitter tol-
erance performance will be degraded. For interfacing
with PECL signal levels, see Applications Information.
Phase Detector
The phase detector incorporated in the MAX3876 pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
_______________________________________________________________________________________ 5
5 Page 
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
Package Information (continued)
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX3876.PDF ] | |
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