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PDF MAX3872EGJ Data sheet ( Hoja de datos )
| Número de pieza | MAX3872EGJ | |
| Descripción | Multirate Clock and Data Recovery with Limiting Amplifier | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-2709; Rev 1; 5/03
EVAALVUAAILTAIOBNLEKIT
Multirate Clock and Data Recovery
with Limiting Amplifier
General Description
The MAX3872 is a compact, multirate clock and data
recovery with limiting amplifier for OC-3, OC-12, OC-24,
OC-48, OC-48 with FEC SONET/SDH and Gigabit
Ethernet (1.25Gbps/2.5Gbps) applications. Without using
an external reference clock, the fully integrated phase-
locked loop (PLL) recovers a synchronous clock signal
from the serial NRZ data input. The input data is then
retimed by the recovered clock, providing a clean data
output. An additional serial input (SLBI±) is available for
system loopback diagnostic testing. Alternatively, this
input can be connected to a reference clock to maintain a
valid clock output in the absence of data transitions. The
device also includes a loss-of-lock (LOL) output.
The MAX3872 contains a vertical threshold control to
compensate for optical noise due to EDFAs in DWDM
transmission systems. The recovered data and clock
outputs are CML with on-chip 50Ω back termination on
each line. Its jitter performance exceeds all
SONET/SDH specifications.
The MAX3872 operates from a single +3.3V supply and
typically consumes 580mW. It is available in a 5mm x
5mm 32-pin thin QFN with exposed-pad package and
operates over a -40°C to +85°C temperature range.
Applications
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
DWDM Transmission Systems
Access Networks
Pin Configuration appears at end of data sheet.
Features
o Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps,
1.244Gbps, 622.08Mbps, 155.52Mbps,
1.25Gbps/2.5Gbps (Ethernet)
o Reference Clock Not Required for Data
Acquisition
o Exceeds ANSI, ITU, and Bellcore SONET/SDH
Jitter Specifications
o 2.7mUIRMS Jitter Generation
o 10mVP-P Input Sensitivity Without Threshold
Adjust
o 0.65UIP-P High-Frequency Jitter Tolerance
o ±170mV Input Threshold Adjust Range
o Clock Holdover Capability Using Frequency-
Selectable Reference Clock
o Serial Loopback Input Available for System
Diagnostic Testing
o Loss-of-Lock (LOL) Indicator
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX3872EGJ -40°C to +85°C 32 QFN
PKG
CODE
G3255-1
Typical Application Circuit
+3.3V
VCC
FILTER
OUT+
CFIL
0.82µF
+3.3V
CAZ
0.1µF
+3.3V +3.3V
FIL VCC_VCO CAZ- CAZ+ FREFSET VCC
SDI+
MAX3745*
OUT-
IN
GND
+3.3V
*FUTURE PRODUCT
SYSTEM
LOOPBACK DATA
SDI-
SLBI+
SDO+
SDO-
SLBI-
MAX3872
SCLKO+
SCLKO-
VCTRL
VREF
SIS LREF LOL RS1 RS2 RATESET GND
+3.3V
CML
CML
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Multirate Clock and Data Recovery
with Limiting Amplifier
Timing Diagrams (continued)
SCLKO+
SDO
tCLK
tCLK-Q
INPUT DATA
DATA
DATA
LOL OUTPUT
LOL ASSERT TIME
ACQUISITION TIME
Figure 3. Definition of Clock-to-Q Delay
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
RECOVERED CLOCK AND DATA
(2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
Figure 4. LOL Assert Time and PLL Acquisition Time
Measurement
Typical Operating Characteristics
RECOVERED CLOCK AND DATA
(2.67Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
200mV/
div
200mV/
div
100ps/div
100ps/div
RECOVERED CLOCK JITTER
(2.488Gbps)
RECOVERED CLOCK JITTER
(622.08Mbps)
10ps/div
TOTAL WIDEBAND RMS JITTER = 1.60ps
PEAK-TO-PEAK JITTER = 12.20ps
10ps/div
TOTAL WIDEBAND RMS JITTER = 2.17ps
PEAK-TO-PEAK JITTER = 15.80ps
JITTER GENERATION
vs. POWER-SUPPLY WHITE NOISE
4.0
OC-48
3.5 PRBS = 223 - 1
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5 10 15 20 25
WHITE-NOISE AMPLITUDE (mVRMS)
30
_______________________________________________________________________________________ 5
5 Page 
Multirate Clock and Data Recovery
with Limiting Amplifier
Input Terminations
The SDI± and SLBI± inputs of the MAX3872 are current-
mode logic (CML) compatible. The inputs all provide
internal 50Ω termination to reduce the required number
of external components. AC-coupling is recommended.
See Figure 8 for the input structure. For additional infor-
mation on logic interfacing, refer to Maxim Application
Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
Output Terminations
The MAX3872 uses CML for its high-speed digital out-
puts (SDO± and SCLKO±). The configuration of the out-
put circuit includes internal 50Ω back terminations to
VCC. See Figure 9 for the output structure. CML outputs
can be terminated by 50Ω to VCC, or by 100Ω differen-
tial impedance. For additional information on logic inter-
facing, refer to Maxim Application Note HFAN 1.0:
Introduction to LVDS, PECL, and CML.
MAX3872
VCC
50Ω 50Ω
SDO+
SDO-
VCC
50Ω 50Ω
SDI+
SDI-
MAX3872
Figure 9. CML Output Model
Applications Information
Clock Holdover Capability
Clock holdover is required in some applications in
which a valid clock must be provided to the upstream
device in the absence of data transitions. To provide
this function, an external reference clock signal must
be applied to the SLBI± inputs and the proper control
signals set (see the Modes of Operation section). To
enter holdover mode automatically when there are no
transitions applied to the SDI± inputs, LOL or the sys-
tem LOS can be directly connected to LREF.
System Loopback
The MAX3872 is designed to allow system loopback
testing. When the device is set for system loopback
mode, the serial output data of a transmitter may be
directly connected to the SLBI inputs to run system
diagnostics. See Table 1 for selecting system loopback
operation mode. While in system loopback mode, LREF
should not be connected to LOL.
Figure 8. CML Input Model
______________________________________________________________________________________ 11
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