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PDF MAX3693ECJ Data sheet ( Hoja de datos )
| Número de pieza | MAX3693ECJ | |
| Descripción | +3.3V / 622Mbps / SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-4775; Rev 1; 4/99
EVAALVUAAILTAIOBNLEKIT
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
General Description
The MAX3693 serializer is ideal for converting 4-bit-
wide, 155Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers a 3.3V PECL serial-data output. A fully integrated
PLL synthesizes an internal 622Mbps serial clock from
a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz ref-
erence clock.
The MAX3693 is available in the extended temperature
range (-40°C to +85°C), in a 32-pin TQFP package.
Features
o Single +3.3V Supply
o 155Mbps (4-bit-wide) Parallel to
622Mbps Serial Conversion
o Clock Synthesis for 622Mbps
o 215mW Power
o Multiple Clock Reference Frequencies
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
o LVDS Parallel Clock and Data Inputs
o Differential 3.3V PECL Serial-Data Output
Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
Ordering Information
PART
MAX3693ECJ
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
(155MHz LVDS CRYSTAL REFERENCE)
OVERHEAD
GENERATION
VCC = +3.3V
PCLKI- PCLKI+ RCLK- RCLK+
PD0+
PD0-
VCC CKSET
FIL+
PD1+
PD1- MAX3693
PD2+
PD2-
PD3+
FIL-
PD3-
PCLKO- PCLKO+ GND
SD- SD+
1µF
VCC = +3.3V
130Ω
1µF
130Ω
VCC = +3.3V
MAX3668
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z0 = 50Ω)
82Ω 82Ω
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________Detailed Description
The MAX3693 serializer comprises a 4-bit parallel input
register, a 4-bit shift register, control and timing logic, a
PECL output buffer, LVDS input/output buffers, and a
frequency-synthesizing PLL (consisting of a phase/
frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and prescaler). This device con-
verts 4-bit-wide, 155Mbps data to 622Mbps serial data
(Figure 1).
The PLL synthesizes an internal 622Mbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz,
77.76MHz, 51.84MHz, or 38.88MHz reference-clock
signal (RCLK).
The incoming parallel data is clocked into the
MAX3693 on the rising transition of the parallel-clock-
input signal (PCLKI). The control and timing logic
ensure proper operation if the parallel-input register is
latched within a window of time that is defined with
respect to the parallel-clock-output signal (PCLKO).
PCLKO is the synthesized 622Mbps internal serial-
clock signal divided by four. The allowable PCLKO-to-
PCLKI skew is 0 to +4ns. This defines a timing window
at about the PCLKO rising edge, during which
a PCLKI rising edge may occur (Figure 2).
PD3+
PD3-
PD2+
PD2-
PD1+
PD1-
PD0+
PD0-
PCLKI+
PCLKI-
RCLK+
RCLK-
LVDS
LVDS
LVDS
4-BIT
PARALLEL
INPUT
REGISTER
LVDS
LVDS
LVDS
PRESCALER
PHASE/FREQ
DETECT
VCO
MAX3693
CONTROL
LVDS
SHIFT
LATCH
4-BIT
SHIFT
REGISTER
PECL
SD+
SD-
Figure 1. Functional Diagram
FIL+ FIL- CKSET
PCLKO+ PCLKO-
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MAX3693ECJ.PDF ] | |
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