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PDF MAX3690 Data sheet ( Hoja de datos )
| Número de pieza | MAX3690 | |
| Descripción | +3.3V / 622Mbps / SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-4774; Rev 1; 4/99
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
General Description
The MAX3690 serializer is ideal for converting 8-bit-
wide, 77Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts TTL clock and
data inputs, and delivers a 3.3V differential PECL serial-
data output. A fully integrated PLL synthesizes an inter-
nal 622MHz serial clock from a low-speed crystal
reference clock (77.76MHz, 51.84MHz, or 38.88MHz).
The MAX3690 is available in the extended-industrial
temperature range (-40°C to +85°C) in a 32-pin TQFP
package.
________________________Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
____________________________Features
o Selectable Reference Clock Frequency:
77.76MHz, 51.84MHz, or 38.88MHz
o Single +3.3V Supply
o 77Mbps (8-bit) Parallel to 622Mbps Serial
Conversion
o Clock Synthesis for 622Mbps Serial Data
o 200mW Power
o TTL Parallel Clock and Data Inputs
o Differential 3.3V PECL Serial-Data Output
PART
MAX3690ECJ
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Pin Configuration appears at end of data sheet.
OVERHEAD
GENERATION
Typical Operating Circuit
38.88MHz TTL CRYSTAL VCC = +3.3V
REFERENCE
PCLKI
RCLK VCC CKSET
1µF 1µF
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PCLKO
MAX3690
FIL+
FIL-
GND SD- SD+
VCC = +3.3V
130Ω
130Ω
VCC = +3.3V
MAX3668
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z0 = 50Ω).
82Ω 82Ω
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLKI
CKSET
RCLK
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
8-BIT
PARALLEL
INPUT
REGISTER
PRE-
SCALER
PHASE/FREQ
DETECT
VCO
Figure 1. Functional Diagram
FIL+ FIL-
CONTROL
TTL
PCLKO
SHIFT
LATCH
8-BIT
SHIFT
REGISTER
MAX3690
SDOH
PECL
SDOL
PCLKO
PCLKI
PD_
tSKEW
tSU
VALID PARALLEL DATA
tH
SD D7 D6 D5 D4 D3 D2 D1 D0
NOTE: PD7 = D7, PD6 = D6, PD5 = D5, PD4 = D4, PD3 = D3, PD2 = D2, PD1 = D1, PD0 = D0
Figure 2. Timing Diagram
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MAX3690.PDF ] | |
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