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PDF MAX3675 Data sheet ( Hoja de datos )
| Número de pieza | MAX3675 | |
| Descripción | 622Mbps / Low-Power / 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX3675 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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19-1258; Rev 2; 11/98
EVALUAATVIOANILKAIBTLMEANUAL
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
_____________________General Description
The MAX3675 is a complete clock-recovery and data-
retiming IC incorporating a limiting amplifier. It is
intended for 622Mbps SDH/SONET applications and
operates from a single +3.3V supply.
The MAX3675 has two differential input amplifiers: one
accepts PECL levels, while the other accepts small-sig-
nal analog levels. The analog inputs access the limiting
amplifier stage, which provides both a received-signal-
strength indicator (RSSI) and a programmable-threshold
loss-of-power (LOP) monitor. Selecting the PECL amplifier
disables the limiting amplifier, conserving power. A loss-
of-lock (LOL) monitor is also incorporated as part of the
fully integrated PLL.
____________________________Features
o Single +3.3V or +5.0V Power Supply
o Complies with ANSI, ITU, and Bellcore
SDH/SONET Specifications
o Low Power: 215mW at +3.3V
o Selectable Data Inputs, Differential PECL or
Analog
o Received-Signal-Strength Indicator (RSSI)
o Loss-of-Power and Loss-of-Lock Monitors
o Differential PECL Clock and Data Outputs
o No External Reference Clock Required
________________________Applications _________________Ordering Information
SDH/SONET Transmission Systems
SDH/SONET Access Nodes
PART
MAX3675ECJ
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Add/Drop Multiplexers
ATM Switches
Digital Cross-Connects
MAX3675EHJ
-40°C to +85°C 5mm 32 TQFP
MAX3675E/D
-40°C to +85°C Dice*
*Contact factory for availability. Dice are designed to operate
from -40°C to +85°C, but are tested and guaranteed only at
Tj = +45°C.
Pin Configuration appears at end of data sheet.
___________________________________________________ Typical Operating Circuit
100pF
PHOTO-
DIODE
+3.3V
+3.3V
CLOL
0.01µF
52.3Ω
1% 2.2µF
0.01µF
VCC
FILT
MAX3664
INREF
OUT+
IN
OUT-
ZO = 50Ω
100Ω
ZO = 50Ω
GND COMP
220pF
+3.3V
0.1µF
INSEL LOL PHADJ+ PHADJ- FIL+
DDI+
DDI-
CIN
0.01µF
ADI+
MAX3675
FIL-
SDO+
SDO-
ADI-
CIN
0.01µF
VCC
SCLKO+
SCLKO-
CFILT OLC+ OLC- GND RSSI INV
VTH LOP
CF
47nF
COLC
33nF
R2
R1
100k
+3.3V
130Ω
ZO = 50Ω
ZO = 50Ω
82Ω
130Ω
82Ω
+3.3V
130Ω
ZO = 50Ω
ZO = 50Ω
82Ω
130Ω
82Ω
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
LOSS-OF-POWER
HYSTERESIS vs. TEMPERATURE
4.0
3.8 223 -1 PATTERN
VCC = +3.3V OR +5.0V
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
-40
-20 0 20 40 60
AMBIENT TEMPERATURE (°C)
80
RECEIVED-SIGNAL-STRENTH INDICATOR
vs. INPUT VOLTAGE
2.8
VCC = +3.3V
2.6
2.4 223 -1 PATTERN
2.2
2.0
1.8
1010 PATTERN
1.6
1.4
1.2
100µ
1m 10m 100m
INPUT VOLTAGE (Vp-p)
1
LOSS-OF-POWER
ASSERT AND RELEASE LEVEL
vs. THRESHOLD VOLTAGE
100m
223 -1 PATTERN
VCC = +3.3V
LOP RELEASE
10m
LOP ASSERT
1m
1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5
DETECTOR THRESHOLD VOLTAGE, VTH (V)
RECEIVED-SIGNAL-STRENGTH INDICATOR
vs. INPUT VOLTAGE
2.8
223 -1 PATTERN
2.6
2.4 VCC = 5.0V
2.2
2.0
1.8
VCC = 3.3V
1.6
1.4
1.2
100µ
1m 10m 100m
INPUT VOLTAGE (Vp-p)
1
SUPPLY CURRENT
vs. TEMPERATURE
90
80
VCC = 5.0V
70
60 VCC = 3.3V
50
40
30
-40
-20 0 20 40 60
AMBIENT TEMPERATURE (°C)
80
_______________________________________________________________________________________ 5
5 Page 
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
Reduced Power Consumption
Without the Limiting Amplifier
The limiting amplifier is biased independently from the
clock recovery circuitry. Grounding INSEL turns off the
limiting amplifier and selects the PECL DDI inputs.
Converting Average Optical Power
to Signal Amplitude
Many of the MAX3675’s specifications relate to input-
signal amplitude. When working with fiber optic
receivers, the input is usually expressed in terms of
average optical power and extinction ratio. The rela-
tions given in Table 2 and Figure 6 are helpful for con-
verting optical power to input signal when designing
with the MAX3675.
In an optical receiver, the input voltage to the limiting
amplifier can be found by multiplying the relationship in
Table 2 by the photodiode responsivity and transim-
pedance amplifier gain.
Optical Hysteresis
Power and hysteresis are often expressed in decibels.
By definition, decibels are always 10log (power). At the
inputs to the MAX3675 limiting amplifier, the power is
VIN2/R. If a receiver’s optical input power (x) increases
by a factor of two, and the preamplifier is linear, then the
voltage at the input to the MAX3675 also increases by a
factor of two.
The optical power increase is 10log(2x / x) = 10log(2) =
+3dB.
At the MAX3675, the voltage increase is:
( )10log 2VIN 2 / R = 10log(22) = 20log(2) = + 6dB
VIN2/ R
Table 2. Optical-Power Relations*
PARAMETER SYMBOL
RELATION
Average
Power
Extinction
Ratio
Optical Power
of a “1”
Optical Power
of a “0”
Signal
Amplitude
PAVE
re
P1
P0
PIN
PAVE =(P0 + P1) / 2
re = P1 / P0
P1 =
2PAVE
re
re + 1
( )P0 = 2PAVE / re +1
( )PIN = P1− P0 = 2PAVE
re − 1
re + 1
*Assuming a 50% average input data duty cycle.
In an optical receiver, the dB change at the MAX3675
always equals 2x the optical dB change.
The MAX3675’s typical voltage hysteresis is 3.0dB. This
provides an optical hysteresis of 1.5dB.
Jitter in Optical Receivers
Timing jitter, edge speeds, aberrations, optical disper-
sion, and attenuation all impact the performance of
high-speed clock recovery for SDH/SONET receivers
(Figure 7). These effects decrease the time available
for error-free data recovery by reducing the received
“eye opening” of non-return-to-zero (NRZ) transmitted
signals.
P1
PAVE
P0
Figure 6. Optical Power Relations
TIME
EYE DIAGRAM WITH NO TIMING JITTER
MIDPOINT
TIME
MIDPOINT
EFFECTS OF TIMING JITTER ON EYE DIAGRAM
TIME
Figure 7. Eye Diagram With and Without Timing Jitter
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX3675.PDF ] | |
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