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PDF MAX3452EEUD Data sheet ( Hoja de datos )
| Número de pieza | MAX3452EEUD | |
| Descripción | 15kV ESD-Protected USB Transceivers | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-2843; Rev 1; 11/03
±15kV ESD-Protected USB Transceivers
General Description
The MAX3450E/MAX3451E/MAX3452E USB-compliant
transceivers interface low-voltage ASICs with USB
devices. The devices fully comply with USB 1.1 and
USB 2.0 when operating at full (12Mbps) and low
(1.5Mbps) speeds. The MAX3450E/MAX3451E/
MAX3452E operate with VL as low as +1.65V, ensuring
compatibility with low-voltage ASICs.
The MAX3450E/MAX3451E/MAX3452E feature a logic-
selectable suspend mode that reduces current con-
sumption to less than 40µA. Integrated ±15kV ESD
protection protects the USB D+ and D- bidirectional
bus connections. The MAX3450E is pin compatible with
Micrel’s MIC2550A. The MAX3451E features an internal
1.5kΩ USB pullup resistor and an enumeration function
that allows devices to logically disconnect while
plugged in. The MAX3452E provides a push-pull bus-
detect (BD) output that asserts high when VBUS is
greater than +4.0V.
The MAX3450E/MAX3451E/MAX3452E operate over the
-40°C to +85°C extended temperature range and are
available in 14-pin TSSOP and 3mm x 3mm 16-pin thin
QFN packages.
Applications
PDAs
PC Peripherals
Cellular Telephones
Data Cradles
MP3 Players
Typical Operating Circuit appears at end of data sheet.
Features
o ±15kV ESD Protection on D+ and D-
o Combined VP and VM Inputs/Outputs
o +1.65V to +3.6V VL Logic Supply Input for
Interfacing with Low-Voltage ASICs
o Enumerate Input Function (MAX3451E)
o Powered from Li+ Battery as Low as +3.1V
(MAX3450E and MAX3451E)
o VBUS Detection (MAX3452E)
o Pin Compatible with Micrel MIC2550A (MAX3450E)
o Internal D+ or D- Pullup Resistor (MAX3451E)
o No Power-Supply Sequencing Required
PART
MAX3450EEUD
MAX3450EETE
MAX3451EEUD
MAX3451EETE
MAX3452EEUD
MAX3452EETE
Ordering Information
TEMP RANGE
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
PIN-PACKAGE
14 TSSOP
16 Thin QFN
14 TSSOP
16 Thin QFN
14 TSSOP
16 Thin QFN
Pin Configurations
TOP VIEW
VL 1
SPD 2
RCV 3
VP 4
VM 5
N.C. 6
GND 7
MAX3450E
MAX3451E
MAX3452E
14 VBUS
13 N.C. *(ENUM) **(BD)
12 VTRM
11 D+
10 D-
9 OE
8 SUS
TSSOP
*MAX3451E ONLY
**MAX3452E ONLY
***CONNECT EXPOSED PADDLE TO GND OR LEAVE FLOATING
16 15 14 13
SPD 1
RCV 2
VP 3
VM 4
MAX3450E
MAX3451E
MAX3452E
***EXPOSED PADDLE
567 8
12 VTRM
11 D+
10 D-
9 OE
3mm x 3mm
THIN QFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
±15kV ESD-Protected USB Transceivers
(VBUS = +5.0V, VL = +3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
SINGLE-ENDED RECEIVER
PROPAGATION DELAY vs. VL
8
CL = 15pF
7
6 TA = +25°C
TA = +85°C
5
4
3 TA = -40°C
2
1
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VL (V)
RISE-/FALL-TIME MATCHING
(FULL SPEED)
MAX3450-52E toc02
CL = 50pF
RISE-/FALL-TIME MATCHING
(LOW SPEED)
MAX3450-52E toc03
CL = 400pF
D+/D-
1V/div
D+/D-
1V/div
20ns/div
100ns/div
OE, VP, AND VM TIMING
MAX3450-52E toc04
CL = 15pF
VP
2V/div
VM
2V/div
20ns/div
OE
5V/div
SUPPLY CURRENT
vs. D+/D- CAPACITANCE
24
22
20
18
16
14
12
10 SPD = VL, fIN = 6MHz
8
6 SPD = GND, fIN = 750kHz
4
2
0
0 50 100 150 200 250 300 350 400
D+/D- CAPACITANCE (pF)
500
450
400
350
300
250
200
150
100
50
0
0
LOGIC SUPPLY CURRENT
vs. D+/D- CAPACITANCE
SPD = VL, fIN = 6MHz
SPD = GND, fIN = 750kHz
50 100 150 200 250 300 350 400
D+/D- CAPACITANCE (pF)
_______________________________________________________________________________________ 5
5 Page 
±15kV ESD-Protected USB Transceivers
+3V
VL
DUT
VP/VM
D+/D-
150Ω
150Ω
VL
560Ω
560Ω
VP/VM
+3V
DUT
D+/D-
OE
D+/D-
tPLZ_DRV
OE
VP/VM CONNECTED TO GND,
D+/D- CONNECTED TO PULLUP
tPZL_DRV
VP/VM CONNECTED TO VL,
D+/D- CONNECTED TO PULLDOWN
OE
VP/VM
tPLZ_SE
OE
D+/D- CONNECTED TO GND,
VP/VM CONNECTED TO PULLUP
tPZL_SE
D+/D- CONNECTED TO +3V,
VP/VM CONNECTED TO PULLDOWN
D+/D-
tPHZ_DRV
tPZH_DRV
Figure 3. Enable and Disable Timing, Driver
VP/VM
tPHZ_SE
tPZH_SE
Figure 5. Enable and Disable Timing, Receiver
+3V
D+ / D-
0
INPUT RISE/FALL TIME < 4ns
MAX3450E
MAX3451E
MAX3452E
TEST
POINT
RCV, VM,
AND VP
CL
(a) LOAD FOR RCV, VM, AND VP
RCV, VM, AND VP
VL
tPLH_RCV,
tPLH_SE
tPHL_RCV,
tPHL_SE
MAX3450E
MAX3451E
MAX3452E
D+ AND D-
(b) LOAD FOR D+/D-
TEST
POINT
24Ω
CL
15kΩ
Figure 4. Timing of D+ and D- to RCV, VM, and VP
Figure 6. Test Circuits
______________________________________________________________________________________ 11
11 Page | ||
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