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PDF DS1236A Data sheet ( Hoja de datos )
| Número de pieza | DS1236A | |
| Descripción | MicroManager Chip | |
| Fabricantes | DALLAS | |
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DS1236A
MicroManager Chip
FEATURES
Holds microprocessor in check during power
transients
Halts and restarts an out-of-control
microprocessor
Monitors pushbutton for external override
Warns microprocessor of an impending power
failure
Converts CMOS SRAM into nonvolatile
memory
Unconditionally write protects memory when
power supply is out of tolerance
Consumes less than 100 nA of battery current
at 25°C
Controls external power switch for high
current applications
Accurate 10% power supply monitoring
Optional 5% power supply monitoring
designated DS1236A-5
Provides orderly shutdown in nonvolatile
microprocessor applications
Supplies necessary control for low-power
“stop mode” in battery operated hand-held
applications
Standard 16-pin DIP or space-saving 16-pin
SOIC
Optional industrial temperature range -40°C
to +85°C
PIN ASSIGNMENT
VBAT 1 16 RST
VCCO 2 15 RST
VCC
GND
PF
PF
WC/SC
RC
3
4
5
6
7
8
14 PBRST
13 CEI
VBAT
VCCO
12 CEO
VCC
11 ST
10 NMI
GND
PF
PF
9 IN
WC/SC
RC
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
RST
RST
PBRST
CEI
CEO
ST
NMI
IN
16-Pin DIP (300-mil)
See Mech. Drawings Section
16-Pin SOIC (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
VBAT
VCCO
VCC
GND
- +3-Volt Battery Input
- Switched SRAM Supply Output
- +5-Volt Power Supply Input
- Ground
PF - Power-Fail (Active High)
PF - Power-Fail (Active Low)
WC/ SC
- Wake-Up Control (Sleep)
RC - Reset Control
IN - Early Warning Input
NMI - Non-Maskable Interrupt
ST - Strobe Input
CEO - Chip Enable Output
CEI - Chip Enable Input
PBRST
- Pushbutton Reset Input
RST - Reset Output (Active Low)
RST - Reset Output (Active High)
DESCRIPTION
The DS1236A MicroManager Chip provides all the necessary functions for power supply monitoring,
reset control, and memory backup in microprocessor-based systems. A precise internal voltage reference
and comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the
microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
write protects external memory. The DS1236A also provides early warning detection of a user-defined
threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset
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DS1236A FUNCTIONAL BLOCK DIAGRAM Figure 1
DS1236A
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DS1236A
the NMI output. In addition, as long as the IN pin is less than VTP, stimulation of the ST pin will result in
additional NMI pulses. In this way, the ST pin can be used to allow the CMOS processor to determine if
the supply voltage, as monitored by the IN pin, is above or below a selected operating value. This is
illustrated in NO TAG. As discussed above, the RC pin determines the timing relationships and levels of
several signals. The following section describes the power-up and power-down timing diagrams in more
detail.
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 9, Figure 10, Figure 11, and
Figure 12. These diagrams show the relative timing and levels in both the NMOS and the CMOS mode
for power-up and down. Figure 9 illustrates the relationship for power-down in CMOS mode. As VCC
falls, the IN pin voltage drops below VTP. As a result, the processor is notified of an impending power
failure via an active NMI , which allows it to enter a sleep mode. As the power falls further, VCC crosses
VCCTP, the power monitor trip point. Since the DS1236A is in CMOS mode, no reset is generated. The
RST voltage will follow VCC down, but will fall no further than VBAT. At this time, CEO is brought high
to write protect the RAM. When the VCC reaches VBAT, a power-fail is issued via the PF and PF pins.
Figure 10 illustrates operation of the power-down sequence in NMOS mode. Once again, as power falls,
an NMI is issued. This gives the processor time to save critical data in nonvolatile SRAM. When VCC
reaches VCCTP, an active RST and RST are given. The RST voltage will follow VCC as it falls. CEO , PF,
and PF will operate in a similar manner to CMOS mode. Notice that the NMI will tri-state to prevent a
loss of battery power.
Figure 11 shows the power-up sequence for the NMOS mode. As VCC slews above VBAT, the PF and PF
pins are deactivated. An active reset occurs as well as an NMI . Although the NMI may be short due to
slew rates, reset will be maintained for the standard tRST timeout period. At a later time, if the IN pin falls
below VTP, a new NMI will occur. If the processor does not issue a ST , a watchdog reset will also occur.
The second NMI and RST are provided to illustrate these possibilities.
Figure 12 illustrates the power-up timing for CMOS mode. The principal difference is that the DS1236A
issues a reset immediately in the NMOS mode. In CMOS mode, a reset is issued when IN rises above
VTP. Depending on the processor type, the NMI may terminate the Stop mode in the processor.
WAKE CONTROL/SLEEP CONTROL
The Wake/Sleep Control input (WC/ SC ) allows the processor to disable all comparators on the DS1236A
before entering the Stop mode. This feature allows the DS1236A, processor, and static RAM to maintain
nonvolatility in the lowest power mode possible. The processor may invoke the sleep mode in battery-
operated applications to conserve battery capacity when an absence of activity is detected. The operation
of this signal is shown in Figure 13. The DS1236A may subsequently be restarted by a high-to-low
transition on the PBRST input through human interface via a keyboard, touchpad, etc. The processor will
then be restarted as the watchdog times out and drives RST and RST active. The DS1236A can also be
started up by forcing the WC/ SC pin high from an external source. Also, if the DS1236A is placed in a
sleep mode by the processor and system power is lost, the DS1236A will wake up the next time VCC rises
above VBAT. These possibilities are illustrated in Figure 14.
When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236A is
disabled, thus leaving the NMI , RST, and RST outputs disabled as well as the ST and IN inputs.
However, a loss of power during a sleep mode will result in an active RST and RST when the RC pin is
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