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Numéro de référence | 7474 | ||
Description | Dual Positive-Edge-Triggered D-Type Flip-Flops | ||
Fabricant | Fairchild | ||
Logo | |||
1 Page
September 1986
Revised July 2001
DM7474
Dual Positive-Edge-Triggered D-Type Flip-Flops
with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D-type flip-flops with complementary outputs. The
information on the D input is accepted by the flip-flops on
the positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated. A LOW logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM7474M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
DM7474N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK
D
Q
Q
LHXXHL
HLXXLH
L L XXHH
(Note 1) (Note 1)
HH ↑ HH L
HH↑ L LH
H H L X Q0 Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↑ = Positive-going transition of the clock.
Q0 = The output logic level of Q before the indicated input conditions were
established.
Note 1: This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to their inactive (HIGH) level.
© 2001 Fairchild Semiconductor Corporation DS006526
www.fairchildsemi.com
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Pages | Pages 5 | ||
Télécharger | [ 7474 ] |
No | Description détaillée | Fabricant |
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