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PDF SCN2681T Data sheet ( Hoja de datos )
| Número de pieza | SCN2681T | |
| Descripción | Dual asynchronous receiver/transmitter DUART | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
SCN2681T
Dual asynchronous receiver/transmitter
(DUART)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
Philips
Semiconductors
1 page  
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCN2681T
PIN DESCRIPTION
MNEMONIC TYPE
NAME AND FUNCTION
D0–D7
I/O Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and
the CPU. D0 is the least significant bit.
CEN
I Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on
D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is high, the DUART places the D0–D7 lines in
the three-state condition.
WRN
I Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the addressed register. The
transfer occurs on the rising edge of the signal.
RDN
I Read Strobe: When low and CEN is also low, causes the contents of the addressed register to be presented on the
data bus. The read cycle begins on the falling edge of RDN.
A0–A3
I Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
I Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the high state,
stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark
(high) state. Clears Test modes, sets MR pointer to MR1.
INTRN
O Interrupt Request: Active-low, open-drain output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.
X1/CLK
I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally
3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
X2 I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it
is permissible to ground it.
RxDA
I Channel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is high, ‘space’ is low.
RxDB
I Channel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is high, ‘space’ is low.
TxDA
O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’
condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is high, ‘space’ is low.
TxDB
O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is high,
‘space’ is low.
OP0
O Output 0: General purpose output, or channel A request to send (RTSAN, active-low). Can be deactivated
automatically on receive or transmit.
OP1
O Output 1: General purpose output, or channel B request to send (RTSBN, active-low). Can be deactivated
automatically on receive or transmit.
OP2
O Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output.
OP3
O Output 3: General purpose output, or open-drain, active-low counter/timer output, or channel B transmitter 1X clock
output, or channel B receiver 1X clock output.
OP4
O Output 4: General purpose output, or channel A open-drain, active-low, RxRDYA/FFULLA output.
OP5
O Output 5: General purpose output, or channel B open-drain, active-low, RxRDYB/FFULLB output.
OP6
O Output 6: General purpose output, or channel A open-drain, active-low, TxRDYA output.
OP7
O Output 7: General purpose output, or channel B open-drain, active-low TxRDYB output.
IP0 I Input 0: General purpose input, or channel A clear to send active-low input (CTSAN). Pin has an internal VCC pull-up
device supplying 1 to 4 mA of current.
IP1 I Input 1: General purpose input, or channel B clear to send active-low input (CTSBN). Pin has an internal VCC pull-up
device supplying 1 to 4 mA of current.
IP2 I Input 2: General purpose input, or counter/timer external clock input. Pin has an internal VCC pull-up device supplying
1 to 4 mA of current.
IP3 I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up
device supplying 1 to 4 mA of current.
IP4 I Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device
supplying 1 to 4 mA of current.
IP5 I Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up
device supplying 1 to 4 mA of current.
IP6 I Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by
the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device
supplying 1 to 4 mA of current.
VCC
GND
I Power Supply: +5V supply input.
I Ground
1998 Sep 04
5
5 Page 
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCN2681T
RxD
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
D1 D2 D3 D4 D5 D6 D7 D8
D6, D7, D8 WILL BE LOST
RxRDY/
FFULL
(OP5)2
RDN
OVERRUN
(SR4)
SD
D1
S = STATUS
D = DATA
D5 WILL
BE LOST
SD
D2
SD SD
D3 D4
RESET BY
COMMAND
RTS1
(OP0)
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1.
2. Shown for OPCR(4) = 1 and MR1(6) = 0.
Figure 11. Receiver Timing
SD00105
MASTER STATION
TxD
BIT 9
ADD#1 1
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
MR1(4–3) = 11
MR1(2) = 1
ADD#1 MR1(2) = 0 D0
BIT 9
D0 0
MR1(2) = 1 ADD#2
BIT 9
ADD#2 1
PERIPHERAL STATION
BIT 9
RxD
0
BIT 9
ADD#1 1
RECEIVER
ENABLED
RxRDY
(SR0)
BIT 9
D0 0
RDN/WRN
MR1(4–3) = 11
ADD#1
SD
D0
S = STATUS
D = DATA
Figure 12. Wake-Up Mode
1998 Sep 04
11
BIT 9
ADD#2 1
BIT 9
0
SD
ADD#2
SD00106
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SCN2681T.PDF ] | |
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