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PDF 74HC4024 Data sheet ( Hoja de datos )
| Número de pieza | 74HC4024 | |
| Descripción | 7-stage binary ripple counter | |
| Fabricantes | Philips | |
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74HC4024
7-stage binary ripple counter
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024
of the 4000B series. The 74HC4024 is specified in compliance with JEDEC
standard no. 7A.
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6).
The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
s Low-power dissipation
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Multiple package options
s Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
3. Applications
s Frequency dividing circuits
s Time delay circuits.
1 page  
Philips Semiconductors
74HC4024
7-stage binary ripple counter
8. Functional description
8.1 Function table
Table 4:
Input
MR
H
L
Function table [1]
CP
X
↑
↓
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH clock transition;
↓ = HIGH-to-LOW clock transition.
9. Limiting values
Output
Qn
L
no change
count
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
−0.5 +7 V
IIK input diode current VI < −0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK
output diode current
VO < −0.5 V or
VO > VCC + 0.5 V
- ±20 mA
IO
output source or sink
VO = −0.5 V to VCC + 0.5 V
current
- ±25 mA
ICC, IGND
Tstg
Ptot
VCC or GND current
storage temperature
power dissipation
DIP14 package
- ±50 mA
−65 +150 °C
[1] -
750 mW
SO14, SSOP14 and
TSSOP14 packages
[2] -
500 mW
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.
9397 750 13813
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 18
5 Page 
Philips Semiconductors
13. Waveforms
74HC4024
7-stage binary ripple counter
MR input
VM
CP input
tPHL
Q0 or Qn
output
tW
1/fmax
trem
tPLH
tW
tTLH
VM
tPHL
VM
tTHL
001aab910
Fig 6.
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (CP) removal time.
VM = 0.5 × VI.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock
pulse width, the output transition times and the maximum clock frequency
PULSE
GENERATOR
VI
VCC
D.U.T.
VO
RT
CL
mna101
Fig 7.
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Load circuitry for switching times
Table 9:
Supply
VCC
2.0 V
4.5 V
6.0 V
5.0 V
Test data
Input
VI
VCC
VCC
VCC
VCC
tr, tf
6 ns
6 ns
6 ns
6 ns
Load
CL
50 pF
50 pF
50 pF
15 pF
9397 750 13813
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 74HC4024.PDF ] | |
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