74FST32517D Datasheet PDF - ON
| Part Number | 74FST32517D | |
| Description | Quad 2:1 Multiplexer/ Demultiplexer Bus Switch | |
| Manufacturers | ON | |
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74FST3257
Quad 2:1 Multiplexer/
Demultiplexer Bus Switch
The ON Semiconductor 74FST3257 is a quad 2:1, high performance
multiplexer/demultiplexer bus switch. The device is CMOS TTL
compatible when operating between 4 and 5.5 Volts. The device
exhibits extremely low RON and adds nearly zero propagation delay.
The device adds no noise or ground bounce to the system.
Features
• RON t 4 W Typical
• Less Than 0.25 ns−Max Delay Through Switch
• Nearly Zero Standby Current
• No Circuit Bounce
• Control Inputs are TTL/CMOS Compatible
• Pin−For−Pin Compatible With QS3257, FST3257, CBT3257
• All Popular Packages: QSOP−16, TSSOP−16, SOIC−16
• All Devices in Package TSSOP are Inherently Pb−Free*
S
1B1
1B2
1A
2B1
2B2
2A
GND
1
2
3
4
5
6
7
8
16 VCC
15 OE
14 4B1
13 4B2
12 4A
11 3B1
10 3B2
9 3A
Figure 1. 16−Lead Pinout
S OE
Function
XH
LL
HL
Disconnect
A = B1
A = B2
Figure 2. Truth Table
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
January, 2005 − Rev. 2
1
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MARKING
DIAGRAMS
16
1
SOIC−16
D SUFFIX
CASE 751B
16
1
FST3257
AWLYWW
16
1
TSSOP−16
DT SUFFIX
CASE 948F
16
1
QSOP−16
QS SUFFIX
CASE 492
16
FST
3257
ALYW
1
16
S3257
ALYW
1
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
PIN NAMES
Pin
OE1, OE2
S0, S1
A
B1, B2, B3, B4
Description
Bus Switch Enables
Select Inputs
Bus A
Bus B
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
74FST3257/D
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74FST3257
AC Loading and Waveforms
FROM
OUTPUT
UNDER
TEST
VI
500 W
CL* 500 W
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*CL = 50 pF
Figure 4. AC Test Circuit
SWITCH
INPUT
10 %
tPLH
tf = 2.5 nS
90 %
1.5 V
90 %
1.5 V
OUTPUT
1.5 V
tf = 2.5 nS
3.0 V
10 %
GND
tPLH
VOH
1.5 V
VOL
Figure 5. Propagation Delays
ENABLE
INPUT
tf = 2.5 nS
90 %
1.5 V
tPZL
OUTPUT
tPZH
OUTPUT
10 % 10 %
1.5 V
1.5 V
tf = 2.5 nS
90 % 3.0 V
1.5 V
GND
tPZL
VOL + 0.3 V
VOL
tPHZL
VOH
VOH − 0.3 V
Figure 6. Enable/Disable Delays
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| Information | Total 8 Pages | |
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