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PDF 74F8962 Data sheet ( Hoja de datos )
| Número de pieza | 74F8962 | |
| Descripción | 9-Bit latched bidirectional Futurebus transceivers open-collector | |
| Fabricantes | Philips | |
| Logotipo |  |
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Philips Semiconductors FAST Products
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
Product specification
74F8962/8963
FEATURES
• Octal latched transceiver
• Drives heavily loaded backplanes with
equivalent load impedances down to 10Ω
• High drive (100mA) open collector drivers
on B port
• Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
• Compatible with IEEE 896 futurebus
standards
• Built–in precision band–gap reference
provides accurate receiver thresholds and
improved noise immunity
• Multiple GND pins minimize ground bounce
• Glitch–free power up/power down
operation
DESCRIPTION
The 74F8962 and 74F8963 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired-OR bus. The B port
inverting drivers are low-capacitance open
collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 150mV
threshold region.
The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching to 9Ω is guaranteed.
The voltage swing is much less for BTL, so is
its receiver threshold region, therefore noise
margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8962 and 74F8963 A ports have TTL
3-state drivers and TTL receivers with a latch
function.
The 74F8963 is the non-inverting version of
74F8962.
TYPE
74F8962
74F8963
TYPICAL PROPAGATION DELAY
6.5ns
5.5ns
TYPICAL SUPPLY CURRENT( TOTAL)
90mA
90mA
ORDERING INFORMATION
DESCRIPTION
44–pin Quad Flat Pack1
44–pin Plastic Leaded Chip Carrier
Note to ordering information
1. Flatpack package is not available at this time.
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F8962Y, N74F8963Y
N74F8962A, N74F8963A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
AI0 – AI8
PNP latched inputs
1.0/0.167
B0 – B8
Data inputs with threshold circuitry
5.0/0.167
OEAB, OEBA
Output enable inputs (active low)
1.0/0.033
LEAB, LEBA
Latch enable inputs (active low)
1.0/0.033
AO0 – AO8
3–state outputs
150/40
B0 – B8
Open collector outputs
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
OC/166.7
LOAD VALUE
HIGH/LOW
20µA/100µA
100µA/100µA
20µA/20µA
20µA/20µA
3mA/24mA
OC/100mA
March 11, 1993
1 853–1425 09230
1 page  
Philips Semiconductors FAST Products
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
Product specification
74F8962/8963
FUNCTION TABLE FOR 74F8962
INPUTS
LATCH STATES
OUTPUTS
OPERATING MODE
AIn Bn* LEAB LEBA OEAB OEBA
AB
BA AOn Bn
HH
L
L
HH
H
H ZX
LL
L
L
HH
L
L Z X B and AO disabled
XX
H
H
H
H
Qn
Qn Z X
H–
L
X
L
H
H
Qn Z L AO 3–state, transparent data from AI to B
L–
L
X
L
H
L
Qn Z H**
XH
X
LHL
Qn
H L X B disabled, transparent data from B to AO
XL
X
LHL
Qn
L HX
XX
H
X
L
H
Qn
Qn Z Qn AO 3–state, latched data to B
XX
X
H
H
L
Qn
Qn Qn X B disabled, latched to AO
XX
H
H
L
L
Qn
Qn Qn Qn Latched state to AO and B
H–
L
L
L
L
H
L H L Read back from AI to B to AO
L–
L
L
L
L
L
H L H** (both latches transparent)
Notes to function table for 74F8962
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. – = Input not externally driven
5. Z = High impedance ”off’ state
6. Qn = High or low voltage level one setup time prior to the low–to–high LEXX transition.
7. H**= Goes to level of pullup voltage.
8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8963
INPUTS
LATCH STATES
OUTPUTS
OPERATING MODE
AIn Bn* LEAB LEBA OEAB OEBA
AB
BA AOn Bn
HH
L
L
HH
L
L ZX
LL
L
L
HH
H
H Z X B and AO disabled
XX
H
H
H
H
Qn
Qn Z X
H–
L
X
L
H
L
Qn Z H AO 3–state, transparent data from AI to B
L–
L
X
L
H
H
Qn Z L
XH
X
LHL
Qn
L H X B disabled, transparent data from B to AO
XL
X
LHL
Qn
H LX
XX
H
X
L
H
Qn
Qn Z Qn AO 3–state, latched data to B
XX
X
H
H
L
Qn
Qn Qn X B disabled, latched to AO
XX
H
H
L
L
Qn
Qn Qn Qn Latched state to AO and B
H–
L
L
L
L
L
L H H** Read back from AI to B to AO
L–
L
L
L
L
H
L L L (both latches transparent)
Notes to function table for 74F8963
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. – = Input not externally driven
5. Z = High impedance ”off” state
6. Qn = High or low voltage level one setup time prior to the low–to–high LEXX transition.
7. H**= Goes to level of pullup voltage.
8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
March 11, 1993
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74F8962.PDF ] | |
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