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Philips - Register stack . 164 RAM 3-State output register

Numéro de référence 74F410
Description Register stack . 164 RAM 3-State output register
Fabricant Philips 
Logo Philips 





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Philips Semiconductors FAST Products
Register stack – 16×4 RAM 3-State output register
Product specification
74F410
FEATURES
Edge triggered output register
ypical access time of 19.5ns
Optimize for register stack operation
3–state outputs
18–pin package
The 74F410 is fully compatible with all TTL
families.
TYPE
74F410
TYPICAL
ACCESS
TIME
19.5ns
TYPICAL
SUPPLY
CURRENT
( TOTAL)
45mA
DESCRIPTION
The 74F410 is a register oriented high speed
64–bit read/write memory organized as
16–words by 4–bits. An edge–triggered 4–bit
output register allows new input data to be
written while previous data is held. 3–state
outputs are provided for maximum versatility.
FUNCTIONAL DESCRIPTION
Write operation – When the three control
inputs, write enable (WE), chip select (CS),
and clock (CP), are low the information on
the data inputs (D0–D3) is written into the
memory location selected by the address
inputs (A0–A3). If the input data changes
while WE, CS, and CP are low, the contents
of the selected memory location follow these
changes provided setup and hold time criteria
are met.
Read operation – When CS is low, WE is
high, and CP goes from low–to–high, the
contents of the memory location selected by
the address inputs (A0–A3) are edge–
triggered into the output register.
When WE is low, CS is low, CP goes from
low–to–high, the data at the data inputs is
edge–triggered into the output register. The
OE input controls the output buffers. When
OE is high the four outputs (Q0–Q3) are in a
high impedance or off state; when OE is low,
the outputs are determined by the state of the
output register.
ORDERING INFORMATION
DESCRIPTION
18–pin plastic DIP (300mil)
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F410N
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
A0 – A3
Address inputs
1.0/1.0
CP Clock pulse input (active rising edge)
1.0/2.0
CS Chip select input (active low)
1.0/2.0
OE Output enable input (active low)
1.0/1.0
WE Write enable input (active low)
1.0/1.0
Q0 – Q3
Data outputs
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/1.2mA
20µA/0.6mA
20µA/0.6mA
3mA/24mA
PIN CONFIGURATION
CS 1
WE 2
A0 3
A1 4
A2 5
A3 6
CP 7
OE 8
GND 9
18 VCC
17 D0
16 Q0
15 D1
14 Q1
13 D2
12 Q2
11 D3
10 Q3
LOGIC SYMBOL
17 15 13 11
D0 D1 D2 D3
3 A0
4 A1
5 A2
6 A3
1 CS
2 WE
7 CP
8 OE
Q0 Q1 Q2 Q3
VCC = Pin 18
GND = Pin 9
16 14 12 10
IEC/IEEE SYMBOL
3
40
5
6
A
0
15
1
2
&
1 G1
7
1C
& G2
8
EN3
17
A1,2D
A3
15
13
11
16
14
12
10
January 8, 1990
1 853-1310 98498

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