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PDF 74F299SJ Data sheet ( Hoja de datos )
| Número de pieza | 74F299SJ | |
| Descripción | Octal Universal Shift/Storage Register with Common Parallel I/O Pins | |
| Fabricantes | National | |
| Logotipo |  |
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May 1995
54F 74F299 Octal Universal Shift Storage Register
with Common Parallel I O Pins
General Description
The ’F299 is an 8-bit universal shift storage register with
TRI-STATE outputs Four modes of operation are possi-
ble hold (store) shift left shift right and load data The par-
allel load inputs and flip-flop outputs are multiplexed to re-
duce the total number of package pins Additional outputs
Q0 – Q7 are provided to allow easy serial cascading A sep-
arate active LOW Master Reset is used to reset the register
Features
Y Common parallel I O for reduced pin count
Y Additional serial inputs and outputs for expansion
Y Four operating modes shift left shift right load and
store
Y TRI-STATE outputs for bus-oriented applications
Y Guaranteed 4000V minimum ESD protection
Commercial
74F299PC
74F299SC (Note 1)
74F299SJ (Note 1)
Military
54F299DM (Note 2)
54F299FM (Note 2)
54F299LM (Note 2)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9515 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9515
TL F 9515 – 4
RRD-B30M75 Printed in U S A
1 page  
AC Electrical Characteristics
Symbol
Parameter
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Maximum Input Frequency
Propagation Delay
CP to Q0 or Q7
Propagation Delay
CP to I On
Propagation Delay
MR to Q0 or Q7
Propagation Delay
MR to I On
Output Enable Time
OE to I On
Output Disable Time
OE to I On
Output Enable Time
Sn to I On
Output Disable Time
Sn to I On
74F
TA e a25 C
VCC e a5 0V
CL e 50 pF
Min Typ Max
70 100
40 70 80
45 65 80
35 70 90
40 85 90
55 75 95
5 5 11 0 10 0
35 60 80
4 0 7 0 10 0
20 45 60
10 40 55
35 90
4 0 10 0
25 60
15 55
54F
TA VCC e Mil
CL e 50 pF
Min Max
85
40 90
45 95
3 5 10 0
4 0 11 0
5 5 12 5
5 5 12 0
30 95
4 0 13 0
15 70
10 65
3 0 10 5
4 0 13 0
15 70
10 65
AC Operating Requirements
Symbol
Parameter
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
tw(L)
trec
Setup Time HIGH or LOW
S0 or S1 to CP
Hold Time HIGH or LOW
S0 or S1 to CP
Setup Time HIGH or LOW
I On DS0 or DS7 to CP
Hold Time HIGH or LOW
I On DS0 or DS7 to CP
CP Pulse Width
HIGH or LOW
MR Pulse Width LOW
Recovery Time MR to CP
74F
TA e a25 C
VCC e a5 0V
Min Max
85
85
0
0
50
50
20
20
50
50
50
70
54F
TA VCC e Mil
Min
10 0
75
0
0
50
50
20
20
50
50
60
12 0
Max
74F
TA VCC e Com
CL e 50 pF
Min Max
70
40 85
45 85
3 5 10 0
4 0 10 0
5 5 10 5
5 5 10 5
35 90
4 0 11 0
20 70
10 65
3 5 10 0
4 0 11 0
25 70
15 65
74F
TA VCC e Com
Min Max
85
85
0
0
50
50
20
20
50
50
50
70
Units
MHz
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74F299SJ.PDF ] | |
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| 74F299SJ | Octal Universal Shift/Storage Register with Common Parallel I/O Pins | National |
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