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PDF 29F800 Data sheet ( Hoja de datos )
| Número de pieza | 29F800 | |
| Descripción | 8 Mbit 1Mb x8 or 512Kb x16 / Boot Block Single Supply Flash Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 29F800 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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M29F800AT
M29F800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Single Supply Flash Memory
PRELIMINARY DATA
s SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
s ACCESS TIME: 70ns
s PROGRAMMING TIME
– 8µs per Byte/Word typical
s 19 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 16 Main Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s TEMPORARY BLOCK UNPROTECTION
MODE
s LOW POWER CONSUMPTION
– Standby and Automatic Standby
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– M29F800AT Device Code: 00ECh
– M29F800AB Device Code: 0058h
TSOP48 (N)
12 x 20mm
44
1
SO44 (M)
Figure 1. Logic Diagram
VCC
19
A0-A18
15
DQ0-DQ14
W DQ15A–1
M29F800AT
E M29F800AB BYTE
G RB
RP
VSS
AI02198B
January 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/21
1 page  
M29F800AT, M29F800AB
Table 4A. Bus Operations, BYTE = VIL
Operation
E GW
Bus Read
VIL VIL VIH
Bus Write
VIL VIH VIL
Output Disable
X VIH VIH
Standby
VIH X
X
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code VIL VIL VIH
Note: X = VIL or VIH.
Address Inputs
DQ15A–1, A0-A18
Data Inputs/Outpu ts
DQ14-DQ8
DQ7-DQ0
Cell Address
Hi-Z Data Output
Command Address
Hi-Z Data Input
X Hi-Z Hi-Z
X Hi-Z Hi-Z
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
20h
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
ECh (M29F800AT)
58h (M29F800AB)
Table 4B. Bus Operations, BYTE = VIH
Operation
E GW
Bus Read
VIL VIL VIH
Bus Write
VIL VIH VIL
Output Disable
X VIH VIH
Standby
VIH X
X
Read Manufacturer
Code
VIL
VIL
VIH
Read Device Code VIL VIL VIH
Note: X = VIL or VIH.
Address Inputs
A0-A18
Cell Address
Command Address
X
X
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
Data Inputs/Outpu ts
DQ15A–1, DQ14-DQ0
Data Output
Data Input
Hi-Z
Hi-Z
0020h
00ECh (M29F800AT)
0058h (M29F800AB)
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, ICC4.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 4A and 4B, Bus Operations, for a summa-
ry. Typically glitches of less than 5ns on Chip En-
able or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 7, Read Mode AC Waveforms,
and Table 11, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
5/21
5 Page 
Table 8. AC Measurement Conditions
Parameter
AC Test Conditions
Load Capacitance (CL)
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
M29F800AT, M29F800AB
M29F800A
70 90
High Speed
Standard
30pF
100pF
≤ 10ns
≤ 10ns
0 to 3V
0.45 to 2.4V
1.5V
0.8V and 2.0V
Figure 5. AC Testing Input Output Waveform
High Speed
3V
0V
Standard
2.4V
0.45V
1.5V
2.0V
0.8V
AI01275B
Figure 6. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3kΩ
OUT
CL = 30pF or 100pF
CL includes JIG capacitance
AI03027
Table 9. Capacitance
(TA = 25 °C, f = 1 MHz)
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
Note: Sampled only, not 100% tested.
Test Condition
VIN = 0V
VOUT = 0V
Min Max Unit
6 pF
12 pF
11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet 29F800.PDF ] | |
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