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Advanced Micro Devices - 4 Megabit (256 K x 16-Bit) CMOS EPROM

Numéro de référence 27C4096
Description 4 Megabit (256 K x 16-Bit) CMOS EPROM
Fabricant Advanced Micro Devices 
Logo Advanced Micro Devices 





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27C4096 fiche technique
FINAL
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time
— Speed options as fast as 90 ns
s Low power consumption
— 100 µA maximum CMOS standby current
s JEDEC-approved pinout
— Plug-in upgrade of 1 Mbit and 2 Mbit EPROMs
— 40-pin DIP/PDIP
— 44-pin PLCC
s Single +5 V power supply
s ±10% power supply tolerance standard
s 100% Flashrite programming
— Typical programming time of 32 seconds
s Latch-up protected to 100 mA from –1 V to
VCC + 1 V
s High noise immunity
GENERAL DESCRIPTION
The Am27C4096 is a 4 Mbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 256
Kwords, operates from a single +5 V supply, has a
static standby mode, and features fast single address
location programming. The Am27C4096 is ideal for use
in 16-bit microprocessor systems. The device is avail-
able in windowed ceramic DIP packages, and plastic
one time programmable (OTP) PDIP and PLCC pack-
ages.
Data can be typically accessed in less than 90 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 125 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 32 seconds.
BLOCK DIAGRAM
OE#
CE#/PGM#
A0–A17
Address
Inputs
VCC
VSS
VPP
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
Data Outputs
DQ0–DQ15
Output
Buffers
Y
Gating
4,194,304
Bit Cell
Matrix
11408F-1
Publication# 11408 Rev: F Amendment/0
Issue Date: May 1998

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