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PDF ACD2203 Data sheet ( Hoja de datos )
| Número de pieza | ACD2203 | |
| Descripción | CATV/TV/Video Downconverter with Dual Synthesizer | |
| Fabricantes | ANADIGICS | |
| Logotipo |  |
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FEATURES
• Integrated Downconverter
• Integrated Dual Synthesizer
• 256 QAM Compatibility
• Single +5 V Power Supply Operation
• Low Power Consumption: <0.6 W
• Low Noise Figure: 8 dB
• High Conversion Gain: 10 dB
• Low Distortion: -53 dBc
• Two-Wire Interface
• Small Size
• -40 °C to +85 °C
ACD2203
CATV/TV/Video Downconverter
with Dual Synthesizer
PRELIMINARY DATA SHEET - Rev 1.3
APPLICATIONS
• Set Top Boxes
• CATV Video Tuners
• Digital TV Tuners
• CATV Data Tuners
• Cable Modems
PRODUCT DESCRIPTION
The ACD2203 uses both GaAs and Si technology
to provide the downconverter and dual synthesizer
functions in a double conversion tuner gain block,
local oscillator, balanced mixer and dual synthesizer.
The specifications meet the requirements of
CATV/TV/Video and Cable Modem Data applications.
The ACD2203 is supplied in a 28 lead SSOP
package and requires a single +5 V supply voltage.
S8 Package
28 Pin SSOP
The IC is well suited for applications where small
size, low cost, low auxiliary parts count and a no-
compromise performance is important. It provides
for cost reduction by lowering the component and
packaged IC count and decreasing the amount of
labor-intensive production alignment steps, while
significantly improving performance and reliability.
RFIN+
RFIN-
Low Noise
VGA
Mixer
VIF+IFOUT+
VIF+IFOUT-
Phase Splitter
TCKT
OSC OUT
Figure 1: Downconverter Block Diagram
RFD
RF2: 64/65
Prescaler
REFIN
REFOUT
Oscillator
RFU
RF1: 64/65
Prescaler
18 Bit RF2
N Counter
15 Bit RF2
R Counter
15 Bit RF1
R Counter
18 Bit RF1
N Counter
RF2
Phase
Detector
RF2
Charge
Pump
CPD
RF1
Phase
Detector
RF1
Charge
Pump
CPU
Clock
Data
AS
2 Bit
A/D
24 Bit
Data Register
Figure 2: Dual Synthesizer Block Diagram
12/2003
1 page  
Table 4: Electrical Specifications - Downconverter Section
(TA = +25 °C (7), VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz)
PARAMETER
MIN TYP MAX UNIT
Conversion Gain (1)
Conversion Gain (2)
8 10 14
11 13 17
dB
SSB Noise Figure (2), (3)
- 4 7 dB
Cross Modulation (2), (4), (6)
-
-56 -53
dBc
3rd Order Intermodulation Distortion
(IMD3) (2), (5), (6)
- - -53 dBc
2-Tone 3rd Order Input Intercept Point
(IIP3) (2), (5), (6)
+12 -
- dBm
LO Phase Noise (@ 10 KHz Offset) (1), (2)
-
-90 -85.5 dBc/Hz
LO Output Power (pin 24) (1), (2)
-10 -5 - dBm
Spurious @ IF Output
LO Signals and Harmonics
Beats Within Output Channel
Other Beats from 2 to 200 MHz
Other Spurious
- -10 - dBm
- -48 -
dBc
- -50 - dBm
- -10 - dBm
IF Supply Current (pin 27 & 28) (1), (2),(6)
- 50 65 mA
Osc/Phase Splitter Supply Current
(pin 25)
- 30 45 mA
Power Consumption
-
400 550
mW
Notes:
(1) As measured in ANADIGICS test fixture with single-ended RF input.
(2) As measured in ANADIGICS test fixture with differential RF inputs.
(3) SSB noise figure will be approximately 3 dB higher with single-ended RF input.
(4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated
99% at 15 kHz.
(5) Two tones: 1085 and 1091 MHz, -15 dBm each.
(6) R1 = 10 Ohms.
(7) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient
Temperature is +25 °C, using the PC Board Layout shown in Figures 24-26.
ACD2203
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
5
5 Page 
ACD2203
LOGIC PROGRAMMING
The ACD2203 includes an interface for a two-wire
serial data control bus that ANADIGICS has
developed for use with its dual PLL synthesizers.
This interface saves one connection between the
host and the dual synthesizer, compared to a
standard CLOCK-DATA-ENABLE three-wire
interface. The interface is optimized for applications
in which the dual synthesizer is a slave receiver
device. Hosts that conform to the I2C-Bus
Specification standard can be used to program a
dual PLL that uses this interface.
Physical Interface
The two-wire interface consists of two digital signal
lines, CLOCK and DATA. The speed of the interface
is nominally 400 kbits/sec. For data transmission,
the signal on the DATA line must be stable when the
CLOCK signal is high, and the state of the data must
change only while the CLOCK signal is low. A logic
level transition on the DATA line during a high
CLOCK signal indicates the beginning or end of a
data transmission, as specified in the following
sections and shown in Figure 21.
Start
Indicator:
CLOCK
DATA
Stop
Indicator:
CLOCK
DATA
Figure 21: Transmission Indicators
Addressing The Dual PLL
The dual PLL monitors the CLOCK and DATA
signals for a Start indication from the host. A Start is
indicated by a high-to-low transition of the DATA
signal while the CLOCK signal is high. Immediately
following the Start indicator, the host sends an 8-bit
address word to the dual PLL. The 8-bit word
required to address the dual PLL is programmable
via a DC voltage level applied to the address select
pin. For example, a voltage of 4V<AS<5V
corresponds to a value of C6h, or 11000110b. (The
MSB is sent first, LSB last.) The Address Select pin
(10) decodes an analog voltage input into two digital
logic output bits AS1 and AS2. The level of a DC
voltage applied to this pin determines the two-bit
logic state, AS2 and AS1 to address the synthesizer.
The software must be programmed with the
corresponding decimal equivalent of the 8b word
selected, as shown in Table 7. Once the dual PLL
has recognized the Start indicator and the
correct address word, it sends an address
acknowledgement to the host by pulling the DATA
line low for one clock pulse. The host can then begin
to send data to program the dual PLL.
Sending Data
After receiving the address byte acknowledgement
from the dual PLL, the host begins sending
programming data in 8-bit words. The MSB is sent
first, and the LSB last. Following the receipt of each
8-bit data word, the dual PLL acknowledges receipt
by pulling the DATA line low for one clock pulse. The
data acknowledgement tells the host it may send
the next data word. For the dual PLL, each group of
three data words (24 bits total) is a significant block
of information used to program one of four registers,
as described in “Programming the Dual PLL.”
Completing Data Transmissions
After sending the final data word, the host sends a
Stop indicator to mark the end of data transmission.
A Stop is indicated by a low-to-high transition of the
DATA signal while the CLOCK signal is held high.
After receiving the Stop indicator, the dual PLL ceases
to send further acknowledgements and begins to
monitor the CLOCK and DATA signals for the next
Start indicator.
Note: The Stop indicator does not directly control
when the programming data is latched or takes
effect; the data takes effect immediately following
the receipt of each three-word block of data, which
represents a complete 24-bit divider register.
Resending Data
If, for some reason, the data transmission fails or is
interrupted, and the dual PLL fails to send an
address word or data word acknowledgement to
the host, the host can resend the data. To resend
data, a new Start indicator and address word must
be sent prior to any data words.
Programming The Dual PLL
Each synthesizer in the dual PLL contains
programmable Reference and Main dividers, which
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ACD2203.PDF ] | |
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