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PDF SED1330 Data sheet ( Hoja de datos )
| Número de pieza | SED1330 | |
| Descripción | CMOS GRAPHIC LCD CONTROLLER | |
| Fabricantes | ETC | |
| Logotipo |  |
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SED1330
CMOS GRAPHIC LCD CONTROLLER
This part is replaced by SED1335. Some pin differences between SED1330 and SED1335 exist. Please check
SED1335 data sheet. S-MOS Systems, Inc., will continue to support existing designs which use SED1330.
s DESCRIPTION
The SED1330 is a CMOS low-power dot matrix liquid crystal graphic display controller. The device stores in
external RAM display data sent by an 8-bit microcomputer, and generates all the signals required by the LCD
drivers. The LSI incorporates an internal character generator ROM which supports user-defined characters
(also an external CGROM can be supported).
The SED1330 can be interfaced to high-speed microprocessors such as the Intel family or Motorola family.
The controller supports a set of rich commands that will allow the user to create a layered display of characters
and graphics.
Also, the controller functions as a pipeline buffer between the MPU and display memory so that low-cost,
medium-speed SRAM can be used.
s FEATURES
• CMOS low-power graphic and character display
controller
• Selectable MPU interface is compatible with both
the Intel family and the Motorola family
• Smooth scrolling support:
Horizontal and vertical scroll
Scrolling of selected areas of the display
• Multimode display:
2 layers of overlapping character and graphics
3 layers of overlapping graphics
• Selectable display synthesis:
Inverse video
Flashing display, cursor on/off/blink
Under and bar cursor, block cursor
Simple animation
• Programmable cursor
• Internal character generator ROM
• Supports external character generator ROM:
8 × 8 or 8 × 16 pixel characters
Allows mixing of ROM and RAM character sets
• Supports 64K bytes of memory:
2 of 32K × 8 100ns SRAM
or 8 of 8K × 8 100ns SRAM
• Display duty .................................. 1/2 to 1/256
• Low power dissipation ................ 5mA (typical)
0.05µA (typical), standby
• Logic power supply ........................ 4.5 to 5.5V
• Package ................ Plastic QFP5-60 pin (FBA)
Plastic QFP6-60 pin (FBB)
s SYSTEM BLOCK DIAGRAM
DATA
CPU CONTROL
SED1330F
68xx
80xx
SRAM
125
LCD
1 page  
• AC CHARACTERISTICS
° System Bus READ/WRITE Timing I (8080)
A0, CS
tAW8
WR, RD
D0~D7
(WRITE)
D0~D7
(READ)
tCYC
tCC
tDS8
tAH8
tDH8
tACC8
tOH8
SED1330
Signal
A0, CS
WR, RD
D0 to D7
Parameter
Address hold time
Address setup time
System cycle time
Control pulse width
Data setup time
Data hold time
RD access time
Output disable time
Symbol
tAH8
tAW8
tCYC
tCC
tDS8
tDH8
tACC8
tOH8
Rating
Min Max
10 —
30 —
*1 —
220 —
120 —
10 —
— 120
10 50
Unit Remark
ns
ns
ns
ns CL = 100 pF
ns + 1TTL
ns
ns
ns
*1. tCYC = 2tc + tCC + tCEA + 75 > tACV + 245 ................ Memory control/movement control commands.
= 4tC + tCC + 30 .............................................. All other commands.
129
5 Page 
° Oscillator Timing
SED1330
VDD
CLO
YDIS
EXT 0O
tOSP
Power ON
Sleep period
tRCL
tOSS
tFCL
tWL tWH
tCL
Signal
CLO
EXT φ0
Parameter
Symbol
Time to stable CLO output
after power-ON
Time to stable CLO after
sleep OFF
External clock rise time
External clock fall time
External clock high-pulse width
External clock low-pulse width
External clock cycle
tOSP
tOSS
tRCL
tFCL
tWH
tWL
tCL
*1. (tC – tRCL – tFCL) × 475/1000 < tWH, tWL
*2. (tC – tRCL – tFCL) × 525/1000 > tWH, tWL
Rating
Min Max
—3
—1
— 15
— 15
*1 *2
*1 *2
100 —
Unit Remark
ms RES = H
20 pF
ms
ns
ns
ns
ns
ns
135
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SED1330.PDF ] | |
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