PDF SAA4955TJ Data sheet ( Hoja de datos )

Número de pieza	SAA4955TJ
Descripción	2.9-Mbit field memory
Fabricantes	Philips
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET SAA4955TJ 2.9-Mbit field memory Product speciﬁcation Supersedes data of 1997 Sep 25 File under Integrated Circuits, IC02 1999 Apr 29 1 page Philips Semiconductors 2.9-Mbit ﬁeld memory Product speciﬁcation SAA4955TJ handbook, halfpage GNDP 1 GND 2 D11 3 40 GNDP 39 GNDO 38 Q11 D10 4 37 Q10 D9 5 36 Q9 D8 6 35 Q8 D7 7 34 Q7 D6 8 33 Q6 D5 9 32 Q5 D4 10 31 Q4 SAA4955TJ D3 11 30 Q3 D2 12 29 Q2 D1 13 28 Q1 D0 14 27 Q0 SWCK 15 26 SRCK RSTW 16 25 RSTR WE 17 24 RE IE 18 23 OE VDD 19 VDD(P) 20 22 VDD(O) 21 VDD(P) MGK675 Fig.2 Pin configuration. 1999 Apr 29 5 5 Page Philips Semiconductors 2.9-Mbit ﬁeld memory Product speciﬁcation SAA4955TJ SYMBOL PARAMETER CONDITIONS MIN. TYP.(1) MAX. UNIT Read cycle timing; note 3 tACC ten(Q) tdis(Q) th(Q) Tcy(SRCK) tW(SRCKH) tW(SRCKL) tsu(RSTR) th(RSTR) tsu(RE) th(RE) tW(REL) tsu(OE) th(OE) tW(OEL) tt access time after SRCK see Fig.10 output enable time after SRCK see Fig.14 output disable time after SRCK note 4; see Fig.14 output hold time after SRCK see Fig.10 SRCK cycle time see Fig.10 HIGH-level pulse width of SRCK see Fig.10 LOW-level pulse width of SRCK see Fig.10 set-up time RSTR see Fig.10 hold time RSTR see Fig.10 set-up time RE see Fig.13 hold time RE see Fig.13 LOW-level pulse width of RE see Fig.13 set-up time OE see Fig.14 hold time OE see Fig.14 LOW-level pulse width of OE see Fig.14 transition time (rise and fall) see Fig.10 −− −− −− 3− 26 − 7− 7− 5− 3− 5− 3− 9− 5− 3− 9− −3 21 21 12 − − − − − − − − − − − − 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1. Typical values are valid for Tamb = 25 °C, VDD = VDD(O) = VDD(P) = 3.3 V, all voltages referenced to GND. See Fig.1 for configuration. 2. The write cycle timing set-up and hold times are related to VIL of the rising edge of SWCK. They are valid for the speciﬁed LOW- and HIGH-level input voltages (VIL and VIH). 3. The read cycle timing set-up and hold times are related to VIL of the rising edge of SRCK. They are valid for the speciﬁed LOW- and HIGH-level input voltages (VIL and VIH). The load on each output is a 30 pF capacitor to ground in parallel with a 218 Ω resistor to 1.31 V. 4. Disable times specified are from the initiating edge until the output is no longer driven by the memory. Disable times are measured by observing the output waveforms. Low values of load resistor and capacitor have to be used to obtain a short time constant. 1999 Apr 29 11 11 Page

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