PDF SA9025 Data sheet ( Hoja de datos )

Número de pieza	SA9025
Descripción	900 MHz transmit modulator and 2.2 GHz fractional-N synthesizer
Fabricantes	Philips
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No Preview Available ! INTEGRATED CIRCUITS SA9025 900 MHz transmit modulator and 2.2 GHz fractional–N synthesizer Objective specification 1997 Aug 01 Philips Semiconductors 1 page Philips Semiconductors 900 MHz transmit modulator and 2.2 GHz fractional–N synthesizer Objective specification SA9025 OPERATING MODES & POWER DOWN CONTROL There are two power saving modes of operation which the SA9025 can be put into, dependent on the status of the system. The intention of these different modes is to disable circuity that is not in use at the time in order to reduce power consumption. During sleep mode, only circuitry which is required to provide a master clock to the digital portion of the system is enabled. During receive mode, circuitry which is used to perform the receive function and provide a master clock is enabled. In transmit mode all the functions of the chip are enabled which are required to perform transmit, receive and provide master clock. SA9025 POWER MODE TRUTH TABLE Sleep Mode Enabled yes no Crystal Oscillator Phase detector and charge pump (transmit offset) VCO SSB Up-converter MCLK Buffer RCLK Buffer ÷M offset loop divider TXLO Buffer RXLO Buffer I/Q Modulator Variable Gain Amp. Control Logic Main Divider Reference Divider Auxiliary Divider Main Phase Detector and charge pump Auxiliary Phase Detector and charge pump Lock Detect Receive Mode yes no Transmit Mode yes no 1997 Aug 01 5 5 Page Philips Semiconductors 900 MHz transmit modulator and 2.2 GHz fractional–N synthesizer Objective specification SA9025 power control, ÷M (offset loop), SE (Tx offset loop synthesizer enable), DUAL mode, Sleep Mode 1 and Sleep Mode 2. The data for FDAC is stored by the B word into a temporary register. When the A word is loaded, the data in this temporary register is loaded together with the A word into the work registers to avoid false temporary main synthesizer output caused by changes in fractional compensation. The A word contains new data for the main divider. The A word is loaded into the working registers only when a main divider synchronization signal is active to avoid phase jumps when VALID DATA CHANGE DATA D0 D1 D21 tSU tH reprogramming the main divider. The synchronization pulse is generated by the main divider when it has reached its terminal count, at which time a main divider output pulse is also sent to the main phase detector. This disables the loading of the A word each main divider cycle during maximum of (NREF / ƒREF) seconds. Therefore, to be sure that the A word will be correctly loaded, the STROBE signal must be high for at least (NREF / ƒREF) seconds. When programming the A word, the main charge pumps on output PHP and PHI are set into the speed–up mode as soon as the A word is latched into the working registers and remain so as long as STROBE is held high. D23 LAST CLOCK D0 FIRST CLOCK CLOCK STROBE CLOCK ENABLED–SHIFT IN DATA tSU tSU CLOCK DISABLED STORE DATA Figure 5. Serial Input Timing Sequence SR01447 1997 Aug 01 11 11 Page

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