|
|
PDF SA25C512 Data sheet ( Hoja de datos )
| Número de pieza | SA25C512 | |
| Descripción | 512Kb EEPROM SPI with 10MHz and Low Standby | |
| Fabricantes | ETC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SA25C512 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
Features
•= Saifun NROM™ Flash Cell
•= Serial Peripheral Interface (SPI) Compatible
•= Supports SPI Modes 0 (0,0) and 3 (1,1)
•= Byte and Page Write Modes (up to 128 bytes)
•= Single Supply Voltage:
– 2.7V to 3.6V (L)
– 4.5V to 5.5V (H)
•= 10MHz Clock Rate
–•= Block Write Protection:
Protect ¼, ½, or Entire Array
•= Write Protect Pin and Write Disable Instructions of both Hardware and
Software Data Protection
•= Self-timed Write Cycle (10mS max)
•= 100,000 Write Cycles (Minimum)
•= 20 Year Data Retention
•= Low-power Standby Current (less than 1µA)
•= 8-SOIC Narrow Package (0.150” Wide Body, JEDEC SOIC)
•= Temperature Range:
– Industrial: -40°C to +85°C
– Commercial: 0°C to +70°C
SA25C512
Data Sheet
512Kb EEPROM SPI
with 10MHz and
Low Standby
General Description
SA25C512 is a 512Kb CMOS non-volatile serial EEPROM,
organized as a 64K x 8-bit memory. The SA25C512 is
available in a space-saving, 8-lead narrow SOIC package. In
addition, it is available in a wide range of voltages – 2.7-3.6 V
and 4.5-5.5 V.
The SA25C512 is enabled through the Chip Select (CSb) pin
and is accessed via a 3-wire interface consisting of Serial Data
Input (SI), Serial Data Output (SO) and Serial Data Clock
(SCK). All write cycles are completely self-timed, and no
separate ERASE cycle is required before write.
(continued)
http://www.saifun.com
Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.
This Data Sheet states Saifun's current technical specifications regarding the Products described herein. This Data Sheet
may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 1909 Rev: 1.1 Amendment: 1
Issue Date: January 27, 2003
1 page  
Ordering Information
SA25C512 Data Sheet
SAIFUN
5
SA 25 C XX L
E YY X
Letter
Blank
X
Package N
MN
Description
Tube
Tape and Reel
8-pin DIP
8-pin SOIC (SO8, 150 mil width)
Temp. Range Blank
E
0 to 70 oC
-40 to +85 oC
Voltage Operating Range L
H
Density 512
C
Interface 25
SA
Figure 2: SA25C512 Ordering Information
2.7 V to 3.6 V
4.5 V to 5.5 V
512 Kb with Write Protect
CMOS Technology
SPI-2 Wires
Saifun Non-Volatile
Memory
5 Page 
Read Status Register (RDSR)
The RDSR instruction provides read
access to the status register. The
BUSY/RDY and WREN statuses of the
device can also be determined by this
instruction. In addition, the Block Write
Protection bits indicate the extent of
protection employed. In order to determine
the status of the device, the value of the
/RDY bit can be continuously polled before
sending any write instruction.
Write Status Register (WRSR)
The WRSR instruction enables the user to
select one of four levels of protection. The
SA25C512 is divided into four array
segments. The top quarter, top half or all of
the memory segments can be protected
(for more details, refer to Table 7). The
data within a selected segment is therefore
read-only.
Table 7. Block Write Protect Bits
Status Register Bits
Level
BP1 BP0
00
0
1/4 0
1
1/2 1
0
All 1
1
Array Addresses
Protected
None
C000 - FFFF
8000 - FFFF
0000 - FFFF
The WRSR instruction (as shown in
Table 8) also allows the user to enable or
disable the WPb pin via the WPBEN bit.
Hardware write protection is enabled when
the WPb pin is low and the WPBEN bit is
1, and disabled when either the WP pin is
high or the WPBEN bit is 0. When the
device is hardware write protected, writes
to the status register are disabled.
SA25C512 Data Sheet
SAIFUN
11
NOTE:
When the WPBEN bit is hardware write
protected, it cannot be changed back
to 0 as long as the WPb pin is held low.
Table 8. WPBEN Operation
WPb WPBEN WEN
Protected
Blocks
Un-
protected
Blocks
Status
Register
X 0 0 Protected Protected Protected
X 0 1 Protected Writable Writable
Low 1
0 Protected Protected Protected
Low 1
1 Protected Writable Protected
High X
0 Protected Protected Protected
High X
1 Protected Writable Writable
Read Sequence (READ)
Reading the SA25C512 via the SO pin
requires the following sequence (for more
details, see Table 9, page 12):
1. After the CSb line is pulled low to select
the device, the READ opcode is
transmitted via the SI line, followed by
the byte address to be read. Upon
completion, any data on the SI line is
ignored.
2. The data (D7-D0) at the specified
address is then shifted out onto the SO
line.
If only one byte is to be read, the CSb line
should be driven high after the data comes
out. The READ sequence can be
continued, as the byte address is
automatically incremented and data
continues to shift out. When the highest
address is reached, the address counter
rolls over to the lowest address, enabling
the entire memory to be read in one
continuous READ cycle.
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet SA25C512.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SA25C512 | 512Kb EEPROM SPI with 10MHz and Low Standby | ETC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |