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PDF OX16C954 Data sheet ( Hoja de datos )
| Número de pieza | OX16C954 | |
| Descripción | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface | |
| Fabricantes | ETC | |
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OX16C954 rev B
High Performance Quad UART with 128-byte FIFOs
Intel / Motorola Bus Interface
FEATURES
• Four independent full-duplex asynchronous 16C950
high performance UART channels
• 128-byte deep FIFO per transmitter and receiver
• UARTs fully software compatible with industry
standard 16C55x type UARTs
• Pin compatible with TL16C554 and ST16C654
• Baud rates up to 15 Mbps in normal mode and
60Mbps in external 1x clock (isochronous) mode
• Readable FIFO levels
• Flexible clock prescaler from 1 to 31.875
• Automated in-band flow control using programmable
Xon/Xoff characters, in both directions
• Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
• Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
REV B ENHANCEMENTS
• Readable in-band and out-of-band flow control status
• Programmable special character detection
• Infra-red (IrDA) receiver and transmitter option
• 5, 6, 7, 8 and 9-bits data framing
• Detection of bad data in the receiver FIFO
• Independent channel reset by software
• Transmitter and receiver can be disabled
• Transmitter idle interrupt
• RS-485 buffer enable signals
• Four byte device ID
• Sleep mode (low operating current)
• System clock up to 60 MHz at 5V, 50 MHz at 3.3V
• 5.0 volt or 3.3v operation*
• 68pin PLCC and 80pin TQFP package options.
*Only the 80pin TQFP package supports operation at 5v or 3.3v.
The OX16C954B is an enhanced, backward-compatible revision of the OX16C954 rev A. It uses the newer core as in the
OX16C950 rev B. The chief enhancements are as follows –
• All known errata fixed
• Full TCR range from 4-16
• Enhanced controls for sleep-mode sensitivity, ability to read FCR and Good Data Status
• 3.3V operation with 80 pin TQFP
• Enhanced isochronous clocking options (optional inversions, DTR/DSR)
Hereafter OX16C954 rev B is simply referred to as OX16C954.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141
© Oxford Semiconductor 2001
OX16C954 rev B Data Sheet R1.0 – November 2001
Part Nos. OX16C954-PCC60-B / OX16C954_TQC60_B
1 page  
OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
1 PERFORMANCE COMPARISON
Feature
Integrated Serial channels
Good-Data status
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OX16C954
4
Yes
Yes
15 Mbps
60 Mbps
128
Yes
Yes
Yes
Yes
128
128
128
Yes
Yes
Yes
248
Yes
Yes
Yes
Yes
Yes
Yes
16C454
4
No
No
115 kbps
n/a
1
No
No
No
No
1
1
n/a
No
n/a
n/a
n/a
No
No
No
No
No
No
16C554
4
No
No
115 kbps
n/a
16
No
No
No
No
4
1
n/a
No
No
No
n/a
No
No
No
No
No
No
16C654
4
No
No
1.5 Mbps
n/a
64
Yes
Yes
Yes
No
4
4
4
No
No
No
2
No
No
No
No
No
Yes
16C750
1
No
No
1 Mbps
n/a
64
Yes
No
Yes
No
4
1
n/a
No
No
No
n/a
No
No
No
No
No
No
Table 1 OX16C954 performance compared with 16C454, 16C554, 16C654 and 16C750 devices
Improvements of the OX16C954 over previous generations of PC UARTs:
Deeper FIFOs:
The OX16C954 offers 128-byte deep FIFOs for the
transmitter and receiver.
Higher data rates:
Transmission and reception baud rates up to 15Mbps. A
flexible clock prescaler offers division ratios of 1 to 31 7/8
in steps of 1/8 using a divide-by-“M N/8” circuitry. The
flexible prescaler allows users to select from a wide variety
of input clock frequencies as well as access to higher baud
rates whilst maintaining compatibility with existing software
drivers (see section 14.2).
External clock option:
The receiver can accept an external clock on the DSR#
input. The transmitter can accept a 1x clock on the RI#
input and/or assert its own (Nx) clock on the DTR# output.
In 1x mode, asynchronous data may be transmitted and
received at speeds up to 60 Mbps (see section 14.6).
Automatic flow control:
The UART automatically handles either or both in-band
(software) flow control (transmitting and receiving Xon/Xoff
characters) and out-of-band (hardware) flow control using
the RTS#/CTS# or DSR#/DTR# modem control lines.
Special character detection:
The receiver can be programmed to generate an interrupt
upon reception of a particular character value.
Power-down:
The device can be placed in ‘sleep mode’ to conserve
power
Readable FIFO levels:
Driver efficiency can be improved by using readable FIFO
levels.
Selectable trigger levels:
The receiver FIFO threshold can be arbitrarily
programmed. The transmitter FIFO threshold and
Data Sheet Revision 1.0
Page 5
5 Page 
OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
TQFP PLCC Dir1 Name
Description
Processor Interface Pins in Motorola Mode (I/M# = ‘0’) Contd.
15 to 11 5 to 1 I/O DB[7:0]
Eight-bit 3-state data bus.
9 to 7 68 to 66
31 18 I R/W#
Read-not-write signal. This signal should be high during read cycles and
low during write cycles.
Serial Port Pins
72 53
69 51
32 19
29 17
O SOUT[3]
O SOUT[2]
O SOUT[1]
O SOUT[0]
Serial data output, Uart 3
Serial data output, Uart 2
Serial data output, Uart 1
Serial data output, Uart 0
72 53 O IrDA_Out[3] UART IrDA data outputs, each Uart, respectively.
69 51 O IrDA_Out[2] Serial data output pins are redefined as IrDA data outputs when MCR[6]
32 19 O IrDA_Out[1] of the corresponding UART channel is set in enhanced mode
29 17 O IrDA_Out[0]
75
56
O RTS[3]#
Active-low Request-To-Send output, for each uart respectively.
66
48
O RTS[2]#
Whenever the automated RTS# flow control is enabled for the
35
22
O RTS[1]#
corresponding channel, the RTS# pin is de-asserted and re-asserted if the
26
14
O RTS[0]#
receiver FIFO reaches or falls below a pair of programmed flow control
thresholds, respectively. The state is controlled by bit 1 of the MCR.
RTS may also be used as a general-purpose output.
77
58
O DTR[3]#
Active-low modem “data-terminal-ready output”, for each uart respectively.
64
46
O DTR[2]#
If automated DTR# flow control is enabled for the corresponding UART
37
24
O DTR[1]#
channel, the DTR# pin is asserted and deasserted if the receiver FIFO
24
12
O DTR[0]#
reaches or falls below the channel’s programmed thresholds, respectively.
The state is set by bit 0 of the MCR. DTR may also be used as a general
purpose output.
77 58 O 485_En[3]
64 46 O 485_En[2] In RS485 half-duplex mode, the DTR# pin of each UART channel may be
37 24 O 485_En[1] programmed to reflect the state of the channel’s transmitter empty bit (or
24 12 O 485_En[0] its inverse) to automatically control the direction of the RS485 transceiver
buffer (see register ACR[4:3])
77 58 O TxClkOut[3]
64 46 O TxClkOut[2] Transmitter 1x (or baud rate generator output) clock. For isochronous
37 24 O TxClkOut[1] applications, the 1x (or Nx) transmitter clock may be asserted on the
24 12 O TxClkOut[0] uart’s DTR# pin (see CKS[5:4]).
4
63 I SIN[3]
Serial data input, UART 3.
57 41 I SIN[2] Serial data input, UART 2.
44 29 I SIN[1] Serial data input, UART 1.
17 7
I SIN[0]
Serial data input, UART 0.
4 63 I
57 41 I
44 29 I
17 7
I
78 59 I
63 45 I
38 25 I
23 11 I
Data Sheet Revision 1.0
IrDA_In[0:3]
IrDA_In[0:3]
IrDA_In[0:3]
IrDA_In[0:3]
CTS[3]#
CTS[2]#
CTS[1]#
CTS[0]#
UART IrDA data inputs, for each uart respectively.
Serial data input pins redefined as IrDA data inputs when MCR[6] of the
corresponding UART channel is set in enhanced mode
Active-low modem “clear-to-send” input, for each uart respectively.
If automated CTS# flow control is enabled for the corresponding UART
channel, upon deassertion of the CTS# pin, the channel’s transmitter will
complete the current character and enter the idle mode until the CTS# pin
is reasserted. Note: flow control characters are transmitted regardless of
the state of the CTS# pin. The state of this pin is reflected in bit 4 of the
MSR.
It can also be used as a general-purpose input.
Page 11
11 Page | ||
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| PDF Descargar | [ Datasheet OX16C954.PDF ] | |
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