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PDF NE5520279A-T1 Data sheet ( Hoja de datos )
| Número de pieza | NE5520279A-T1 | |
| Descripción | NECS 3.2 V / 2 W / L&S BAND MEDIUM POWER SILICON LD-MOSFET | |
| Fabricantes | NEC | |
| Logotipo |  |
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NEC'S 3.2 V, 2 W, L&S BAND NE5520279A
MEDIUM POWER SILICON LD-MOSFET
FEATURES
• LOW COST PLASTIC SURFACE MOUNT PACKAGE:
5.7x5.7x1.1 mm MAX
• HIGH OUTPUT POWER:
+32 dBm TYP
• HIGH LINEAR GAIN:
10 dB TYP @ 1.8 GHz
• HIGH POWER ADDED EFFICIENCY:
45% TYP at 1.8 GHz
• SINGLE SUPPLY:
2.8 to 6.0 V
OUTLINE DIMENSIONS (Units in mm)
PACKAGE OUTLINE 79A
4.2 MAX.
(Bottom View)
1.5±0.2
Source
Source
Gate
Drain
Gate
Drain
0.4±0.15
5.7 MAX.
0.8 MAX.
3.6±0.2
DESCRIPTION
NEC's NE5520279A is an N-Channel silicon power laterally
diffused MOSFET specially designed as the power ampliÞer
for mobile and Þxed wireless applications. Die are manu-
factured using NEC's NEWMOS technology (NEC's 0.6 µm
WSi gate lateral MOSFET) and housed in a surface mount
package.
APPLICATIONS
• DIGITAL CELLULAR PHONES:
3.2 V DCS1800 Handsets
• 0.7-2.5 GHz FIXED WIRELESS ACCESS
• W-LAN
• SHORT RANGE WIRELESS
• RETAIL BUSINESS RADIO
• SPECIAL MOBILE RADIO
ELECTRICAL CHARACTERISTICS (TA = 25°C)
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
CHARACTERISTICS
UNITS
POUT Output Power
dBm
GL Linear Gain
dB
ηADD Power Added EfÞciency
%
ID Drain Current
mA
IGSS Gate-to-Source Leakage Current
nA
IDSS Saturated Drain Current
(Zero Gate Voltage Drain Current)
nA
VTH Gate Threshold Voltage
V
gm Transconductance
S
BVDSS Drain-to-Source Breakdown Voltage
V
RTH Thermal Resistance
°C/W
NE5520279A
79A
MIN TYP MAX
30.5 32.0
10
40 45
800
100
100
1.0 1.4
1.3
15 18
1.9
8
Notes:
1. DC performance is 100% testing. RF performance is testing several samples per wafer.
Wafer rejection criteria for standard devices is 1 reject for several samples.
2. Pin = 5 dBm
TEST CONDITIONS
f = 1.8 GHz, VDS = 3.2 V,
IDSQ = 700 mA, PIN = 25 dBm, except
PIN = 5 dBm for Linear Gain
VGS = 5.0 V
VDS = 6.0 V
VDS = 3.5 V, IDS = 1 mA
VDS = 3.5 V, IDS = 700 mA
IDSS = 10 µA
Channel-to-Case
California Eastern Laboratories
1 page  
APPLICATION CIRCUIT (2.40-2.48 GHz)
C3
C9
C11
GND
P1
VG J3
VD J4
C2
C8
C10
J1
RF IN
C13
C12
IN
R1 C14
C15
C5
C6
U1 C1
C4
OU
J2
RF OUT
er=4.2
t=0.028
500855
NE5520279A
P.C.B. LAYOUT (Units in mm)
79A PACKAGE
4.0
1.7
Drain
Gate
Source
0.5
Through hole φ 0.2 × 33
0.5
6.1
5.74mm
.30mm
.63mm
J3
+Vg
C13 C11 C9 C3
C2 C8 C10 C12
J4
+Vd
J1
RF INPUT
C5
R1
NE5520279A
C7 C14
C4 C15
C1
NE5520279A PARTS LIST
1 SD-500881
1 TF-100637
4
2 MA101J
1 MCR03J200
1 600S2R7CW
1 600S2R2BW
1 600S1R2BW
2 600S5R6CW
1 600S3R3CW
2 TAJB475K010R
2 GRM40X7R104K025BL
2 GRM40C0G102J050BD
1 NE5520279A
1 703401
1 1250-003
2 2052-5636-02
1 FD-500855B
C2,C3
R1
C4
C15
C14
C1, C5
C6
C12, C13
C10, C11
C8, C9
U1
P1
J3, J4
J1, J2
PCB
SCHEMATIC DIAGRAM NE5520279A-EVAL
TEST CIRCUIT BLK
2-56 x 3/16 PHILLIPS PAN HEAD
CASE 1 100pF CAP MURATA
0603 20 OHM RESISTOR ROHM
0603 2.7pF CAP ATC
0603 2.2pF CAP ATC
0805 1.2pF CAP ATC
0603 5.6pF CAP ATC
0603 3.3pF CAP ATC
CASE B 4.7 uF CAP AVX
0805 .1uF CAP MURATA
0805 1000 pF CAP MURATA
IC NEC
GROUND LUG CONCORD
FEEDTHRU MURATA
FLANGE MOUNT JACK RECEPTACLE
S-BAND MODULE FABRICATION DRAWING
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J2
RF OUTPUT
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet NE5520279A-T1.PDF ] | |
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