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PDF NE5020F Data sheet ( Hoja de datos )

Número de pieza NE5020F
Descripción 10-Bit mP-compatible D/A converter
Fabricantes Philips 
Logotipo Philips Logotipo



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Philips Semiconductors Linear Products
10-Bit µP-compatible D/A converter
Product specification
NE5020
DESCRIPTION
The NE5020 is a microprocessor-compatible monolithic 10-bit
digital-to-analog converter subsystem. This device offers 10-bit
resolution and ±0.1% accuracy and monotonicity guaranteed over
full operating temperature range.
Low loading latches, adjustable logic thresholds, and addressing
capability allow the NE5020 to directly interface with most
microprocessor- and logic-controlled systems.
The NE5020 contains internal voltage reference, DAC switches and
resistor ladder. Also, the input buffer and output summing amplifier
are included. In addition, the matched application resistors for
scaling either unipolar or bipolar output values are included on a
single monolithic chip.
The result is a near minimum component count 10-bit resolution
DAC system.
FEATURES
10-bit resolution
Guaranteed monotonicity over operating range
±0.1% relative accuracy
Unipolar (0V to +10V) and bipolar (± 5V) output range
Logic bus compatible
5µs settling time
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line Package (CERDIP)
24-Pin Plastic Dual In-Line Package (DIP)
PIN CONFIGURATION
F, N Packages
DIGITAL GND
DB0(LSB)
DB1
DB2
DB3
1
2
3
4
5
DB4 6
DB5 7
DB6 8
DB7(MSB) 9
NC 10
11
LE1 12
24 ANALOG GND
23 AMP COMP
22 SUM MODE
21 VCC+
20 VOUT
19 VCC–
18 BIPOLAR OFFSET R
17 +VREFIN
16 –VREFIN
15 VREFOUT
14 VREFADJ
13 LE2
APPLICATIONS
Precision 10-bit D/A converters
10-bit analog-to-digital converters
Programmable power supplies
Test equipment
Measurement instruments
TEMPERATURE RANGE
0 to 70°C
0 to 70°C
ORDER CODE
NE5020F
NE5020N
DWG #
0588B
0412A
August 31, 1994
757 853-0392 13721

1 page




NE5020F pdf
Philips Semiconductors Linear Products
10-Bit µP-compatible D/A converter
Product specification
NE5020
MSB
LE2 LE1
LSB
VCC+
0.47µF
5.000V
11 10 9 8 7 6 5 4 3 2
12
13
17 VREF IN
15 VREF OUT
14 5020
19 18
21
DIG GND 1
ANA GND 24
–VREF IN 16
VOUT 20
SUM 22
AMP 23
COMP
OUTPUT
30pF
5k
100pF
MSB
LE2 LE1
LSB
VCC+
0.47µF
11 10 9 8 7 6 5 4 3 2
12
13
17
21
DIG GND 1
ANA GND 24
15
14
5020 –VREF IN 16
VOUT 20
SUM 22
19 18
AMP 23
COMP
OUTPUT
30pF
5k
100pF
0.1µF
VCC–
Figure 1. DC Parametric Test Configuration
MSB
LE2 LE1
VCC–
0.1µF
Figure 2. AC Parametric Test Configuration
LSB
VCC+
0.47µF
10k
10T 80k
FULL SCALE
ADJUST
11 10 9 8 7 6 5 4 3 2
12
13
17 VREF IN
15 VREF OUT
14
5020
VREF ADJ
19 18
21
DIG GND 1
ANA GND 24
–VREF IN 16
VOUT 20
SUM 22
AMP 23
COMP
30pF OUTPUT
100pF
5k
VCC–
0.1µF
VCC+
20k
10T
VCC–
1M
ZERO SCALE
ADJUST
Figure 3. Full-/Zero-Scale Adjust — Unipolar Output (0–10V)
MSB
LE2 LE1
LSB
VCC+
0.47µF
11 10 9 8 7 6 5 4 3 2
12
13
17 VREF IN
21
DIG GND 1
ANA GND 24
10k
10T
15 VREF OUT
14
5020
VREF ADJ
–VREF IN 16
VOUT 20
80k
30pF OUTPUT
SUM 22
5k
BIP OFF
AMP 23
19 18
COMP
100pF
VCC–
0.1µF
VCC+
20k
10T
VCC–
1M
FULL SCALE
ADJUST
Figure 4. Bipolar Output Operation (–5 to +5V)
August 31, 1994
761

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