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PDF NDS336P Data sheet ( Hoja de datos )
| Número de pieza | NDS336P | |
| Descripción | P-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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June 1997
NDS336P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
SuperSOTTM-3 P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications such as notebook computer power management,
portable electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are needed
in a very small outline surface mount package.
-1.2 A, -20 V, RDS(ON) = 0.27 Ω @ VGS= -2.7 V
RDS(ON) = 0.2 Ω @ VGS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface Mount
package.
________________________________________________________________________________
D
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Maximum Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
GS
NDS336P
-20
±8
-1.2
-10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
NDS336P Rev. E
1 page  
Typical Electrical Characteristics (continued)
1.06
1.04
ID = - 250µA
1.02
1
0.98
0.96
-50
-25
0
25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature.
5
VGS = 0V
1
0.1
0.01
TJ = 125°C
25°C
-55°C
0.001
0.0001
0.2
0.4 0.6 0.8
1
-V SD , BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 8. Body Diode Forward Voltage Variation
with Source Current and
Temperature.
800
500
Ciss
300
200 Coss
100
f = 1 MHz
60 VGS = 0V
40
0.1
0.2
0.5 1
2
5
-VDS , DRAIN TO SOURCE VOLTAGE (V)
Crss
10 20
Figure 9. Capacitance Characteristics.
5
ID = -1.2A
4
3
VDS = -5V
-10V
-15V
2
1
0
0246
Qg , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics.
8
VIN
VGS
RGEN
G
VDD
RL
D
V OUT
DUT
S
t d(on)
ton
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDS336P Rev. D
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NDS336P.PDF ] | |
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