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Fairchild - N-Channel Enhancement Mode Field Effect Transistor

Numéro de référence NDP7052
Description N-Channel Enhancement Mode Field Effect Transistor
Fabricant Fairchild 
Logo Fairchild 





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NDP7052 fiche technique
June 1997
NDP7052 / NDB7052
N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process has
been especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as automotive, DC/DC converters, PWM
motor controls, and other battery powered circuits where fast
switching, low in-line power loss, and resistance to transients
are needed.
75 A, 50 V. RDS(ON) = 0.01 @ VGS= 10 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low RDS(ON).
TO-220 and TO-263 (D2PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol Parameter
NDP7052
VDSS Drain-Source Voltage
VDGR
Drain-Gate Voltage (RGS < 1 M)
VGSS Gate-Source Voltage - Continuous
- Nonrepetitive (tP < 50 µs)
ID Drain Current - Continuous
- Pulsed
PD Total Power Dissipation @ TC = 25°C
Derate above 25°C
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJC
Rθ JA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
© 1997 Fairchild Semiconductor Corporation
S
50
50
±20
±40
75
225
150
1
-65 to 175
NDB7052
1
62.5
Units
V
V
V
A
W
W/°C
°C
°C/W
°C/W
NDP7052 Rev.B1

PagesPages 6
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