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Fairchild - P-Channel Logic Level Enhancement Mode Field Effect Transistor

Numéro de référence NDC652P
Description P-Channel Logic Level Enhancement Mode Field Effect Transistor
Fabricant Fairchild 
Logo Fairchild 





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NDC652P fiche technique
March 1996
NDC652P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management and other
battery powered circuits where fast high-side switching,
and low in-line power loss are needed in a very small
outline surface mount package.
Features
-2.4A, -30V. RDS(ON) = 0.18@ VGS = -4.5V
RDS(ON) = 0.11@ VGS = -10V.
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
____________________________________________________________________________________________
43
52
61
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to-Case
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDC652P
-30
-20
-2.4
-10
1.6
1
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
NDC652P Rev. D1

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