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PDF NDC632P Data sheet ( Hoja de datos )
| Número de pieza | NDC632P | |
| Descripción | P-Channel Logic Level Enhancement Mode Field Effect Transistor | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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June1996
NDC632P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode
power field effect transistors are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as notebook computer power
management and other battery powered circuits
where fast high-side switching, and low in-line power
loss are needed in a very small outline surface
mount package.
Features
-2.7A, -20V. RDS(ON) = 0.14Ω @ VGS = -4.5V
RDS(ON) = 0.2Ω @ VGS = -2.7V.
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
___________________________________________________________________________________________
SuperSOTTM-6
43
52
61
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDC632P
-20
-8
-2.7
-10
1.6
1
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
NDC632P Rev. B1
1 page  
Typical Electrical Characteristics (continued)
1.1
ID = -250µA
1.05
1
0.95
0.9
-50 -25 0 25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature.
15
5 VGS =0V
1
TJ = 125°C
0.1
25°C
-55°C
0.01
0.001
0.0001
0
0.2 0.4 0.6 0.8 1 1.2
-VSD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
1000
500
300
200
Ciss
Coss
100
50
0.1
f = 1 MHz
VGS = 0V
0.2 0.5 1
5
-V DS , DRAIN TO SOURCE VOLTAGE (V)
Crss
10 15 20
Figure 9. Capacitance Characteristics.
5
ID = -2.7A
4
3
VDS = -5V
-10V
-15V
2
1
0
0 2 4 6 8 10
Q g , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics.
V IN
VG S
RGEN
G
-VD D
RL
D
V OUT
DUT
S
Figure 11. Switching Test Circuit.
t d(on)
ton
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
50%
PULSE WIDTH
INVERTED
Figure 12. Switching Waveforms.
NDC632P Rev. B1
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet NDC632P.PDF ] | |
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