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PDF NDB6030L Data sheet ( Hoja de datos )

Número de pieza NDB6030L
Descripción N-Channel Logic Level Enhancement Mode Field Effect Transistor
Fabricantes Fairchild 
Logotipo Fairchild Logotipo



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No Preview Available ! NDB6030L Hoja de datos, Descripción, Manual

June 1996
NDP6030L / NDB6030L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited
for low voltage applications such as DC/DC converters
and high efficiency switching circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
52 A, 30 V. RDS(ON) = 0.0135 @ VGS=10 V
RDS(ON) = 0.020 @ VGS=4.5 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low RDS(ON).
175°C maximum junction temperature rating.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
TC = 25°C unless otherwise noted
NDP6030L
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
PD Total Power Dissipation @ TC = 25°C
Derate above 25°C
TJ,TSTG
TL
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
THERMAL CHARACTERISTICS
RθJC
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
30
± 16
52
156
75
0.5
-65 to 175
275
NDB6030L
2
62.5
© 1998 Fairchild Semiconductor Corporation
Units
V
V
A
W
W/°C
°C
°C
°C/W
°C/W
NDP6030L Rev.E

1 page




NDB6030L pdf
Typical Electrical Characteristics (continued)
1.15
I D = 250µA
1.1
1.05
1
0.95
0.9
-50 -25
0 25 50 75 100 125 150 175
TJ , JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage
Variation with Temperature.
50
20 VGS = 0V
5
1
0.1
0.01
TJ= 125°C
25°C
-55°C
0.001
0.0001
0
0.2 0.4 0.6 0.8 1 1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 8. Body Diode Forward Voltage Variation
with Source Current and
Temperature.
5000
3000
2000
1000
Ciss
Coss
500
f = 1 MHz
300 VGS = 0V
Crss
200
0.1
0.2
0.5 1
2
5 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 9. Capacitance Characteristics.
10
ID = 52A
8
6
VDS = 10V
20V
15V
4
2
0
0 10 20 30 40
Qg , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics.
50
VIN
VGS
RGEN
G
VDD
RL
D
VOUT
DUT
S
Figure 11. Switching Test Circuit.
t d(on)
t on
tr
90%
td(off)
toff
tf
90%
VO U T
VIN
10%
10%
50%
10%
90%
INVERTED
50%
PULSE WIDTH
Figure 12. Switching Waveforms.
NDP6030L Rev.E

5 Page





NDB6030L arduino
TO-263AB/D2PAK Tape and Reel Data and Package Dimensions, continued
TO-263AB/D2PAK (FS PKG Code 45)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 1.4378
August 1998, Rev. A

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