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PDF NCP1207P Data sheet ( Hoja de datos )

Número de pieza NCP1207P
Descripción PWM Current-Mode Controller for Free Running Quasi-Resonant Operation
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NCP1207
PWM Current−Mode
Controller for Free Running
Quasi−Resonant Operation
The NCP1207 combines a true current mode modulator and a
demagnetization detector to ensure full borderline/critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi−Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 8.0 ms
timer prevents the free−run frequency to exceed 100 kHz (therefore
below the 150 kHz CISPR−22 EMI starting limit), while the skip
adjustment capability lets the user select the frequency at which the
burst foldback takes place.
The Dynamic Self−Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1207. This feature is particularly useful in applications
where the output voltage varies during operation (e.g. battery
chargers). Due to its high−voltage technology, the IC is directly
connected to the high−voltage DC rail. As a result, the short−circuit
trip point is not dependent upon any VCC auxiliary level.
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast
Overvoltage Protection (OVP). Once an OVP has been detected, the
IC permanently latches−off.
Finally, the continuous feedback signal monitoring implemented
with an overcurrent fault protection circuitry (OCP) makes the final
design rugged and reliable.
Features
Free−Running Borderline/Critical Mode Quasi−Resonant Operation
Current−Mode with Adjustable Skip−Cycle Capability
No Auxiliary Winding VCC Operation
Auto−Recovery Overcurrent Protection
Latching Overvoltage Protection
External Latch Triggering, e.g. Via Overtemperature Signal
500 mA Peak Current Source/Sink Capability
Internal 1.0 ms Soft−Start
Internal 8.0 ms Minimum TOFF
Adjustable Skip Level
Internal Temperature Shutdown
Direct Optocoupler Connection
SPICE Models Available for TRANsient Analysis
Pb−Free Package is Available
Typical Applications
AC/DC Adapters for Notebooks, etc.
Offline Battery Chargers
Consumer Electronics (DVD Players, Set−Top Boxes, TVs, etc.)
Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
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8
1
8
1
SOIC−8
D1, D2 SUFFIX
CASE 751
MARKING
DIAGRAMS
8
1207
ALYW
1
PDIP−8
N SUFFIX
CASE 626
8
1
1207P
AWL
YYWW
1207/P = Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
DMG 1
FB 2
CS 3
GND 4
8 HV
7 NC
6 VCC
5 Drv
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
NCP1207DR2
SOIC−8 2500/Tape & Reel
NCP1207DR2G SOIC−8 2500/Tape & Reel
(Pb−Free)
NCP1207P
PDIP−8
50 Units/Tube
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
June, 2004 − Rev. 6
1
Publication Order Number:
NCP1207/D

1 page




NCP1207P pdf
NCP1207
TYPICAL CHARACTERISTICS
(TJ = −40°C to 125°C)
13.2
7 12.8
12.4
12.0
11.6
11.2
10.8
11.2
10.8
10.4
10.0
9.6
9.2
10.4
−50 −25
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 3. VCC Increasing Level at which the
Current Source Turns−off versus Temperature
1.60
1.40
8.8
−50
−25
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 4. VCC Decreasing Level at which the
Current Source Turns−on versus Temperature
2.30
2.10
1.20 1.90
1.00 1.70
0.80 1.50
0.60 1.30
0.40
−50 −25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 5. Internal IC Consumption, No Output
Load on Pin 5 versus Temperature
12
11
10
9
8
7
6
5
4
3
2
−50 −25
0 25 50 75
TEMPERATURE (°C)
100 125
Figure 7. Internal Startup Current Source,
VCC = 10 V versus Temperature
1.10
−50
−25
0 25 50 75
TEMPERATURE (°C)
100 125
Figure 6. Internal IC Consumption, Output
Load on Pin 5 versus Temperature
1.20
1.15
1.10
1.05
1.00
0.95
0.90
−50
−25
0 25 50 75
TEMPERATURE (°C)
100 125
Figure 8. Maximum Internal Current Setpoint
versus Temperature
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NCP1207P arduino
NCP1207
Demagnetization Detection
The core reset detection is done by monitoring the voltage
activity on the auxiliary winding. This voltage features a
FLYBACK polarity. The typical detection level is fixed at
50 mV as exemplified by Figure 21.
7.0
400
300
200
5.0 POSSIBLE
RE−STARTS
3.0
100
0
1.0
0V
−1.0
50 mV
Figure 21. Core reset detection is done through a
dedicated auxiliary winding monitoring
TO INTERNAL
COMPARATOR
Resd
2
1
1
Rdem
5
4
Rint
ESD2
ESD1
Aux
Resd + Rint = 28 k
43
Figure 22. Internal Pad Implementation
An internal timer prevents any re−start within 8.0 ms
further to the driver going−low transition. This prevents the
switching frequency to exceed (1 / (TON + 8.0 ms)) but also
avoid false leakage inductance tripping at turn−off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
The 1207 demagnetization detection pad features a
specific component arrangement as detailed by Figure 22. In
this picture, the zener diodes network protect the IC against
any potential ESD discharge that could appear on the pins.
The first ESD diode connected to the pad, exhibits a parasitic
capacitance. When this parasitic capacitance (10 pF
typically) is combined with Rdem, a re−start delay is created
and the possibility to switch right in the drain−source wave
exists. This guarantees QR operation with all the associated
benefits (low EMI, no turn−on losses etc.). Rdem should be
calculated to limit the maximum current flowing through
pin 1 to less than +3 mA/−2 mA. If during turn−on, the
auxiliary winding delivers 30 V (at the highest line level),
then the minimum Rdem value is defined by:
(30 V + 0.7 V) / 2 mA = 14.6 kW.
This value will be further increased to introduce a re−start
delay and also a slight filtering in case of high leakage
energy.
Figure 23 portrays a typical VDS shot at nominal output
power.
Figure 23. The NCP1207 Operates in
Borderline / Critical Operation
Overvoltage Protection
The overvoltage protection works by sampling the plateau
voltage 4.5 ms after the turn−off sequence. This delay
guarantees a clean plateau, providing that the leakage
inductance ringing has been fully damped. If this would not
be the case, the designer should install a small RC damper
across the transformer primary inductance connections.
Figure 24 shows where the sampling occurs on the auxiliary
winding.
SAMPLING HERE
8.0
6.0
4.0
2.0
4.5 ms
0
Figure 24. A voltage sample is taken 4.5 ms after
the turn−off sequence
When an OVP condition has been detected, the NCP1207
enters a latch−off phase and stops all switching operations.
The controller stays fully latched in this position and the
DSS is still active, keeping the VCC between 5.3 V/12 V as
in normal operations. This state lasts until the VCC is cycled
down 4 V, e.g. when the user unplugs the power supply from
the mains outlet.
By default, the OVP comparator is biased to a 5 V
reference level and pin 1 is routed via a divide by 1.44
network. As a result, when Vpin1 reaches 7.2 V, the OVP
comparator is triggered. The threshold can thus be adjusted
by either modifying the power winding to auxiliary winding
turn ratios to match this 7.2 V level, or insert a resistor from
pin1 to ground to cope with your design requirement.
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