|
|
PDF NCN6004AFTBR2 Data sheet ( Hoja de datos )
| Número de pieza | NCN6004AFTBR2 | |
| Descripción | Dual SAM/SIM Interface Integrated Circuit | |
| Fabricantes | ON | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NCN6004AFTBR2 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
NCN6004A
Dual SAM/SIM Interface
Integrated Circuit
The NCN6004A is an interface IC dedicated for Secured Access
Module reader/writer applications. It allows the management of two
external ISO/EMV cards thanks to a simple and flexible
microcontroller interface. Several NCN6004A interfaces can share a
single data bus, assuming the external MPU provides the right Chip
Select signals to identify each IC connected on the bus. A built in
accurate protection system guarantees timely and controlled shutdown
in the case of external error conditions.
On top of that, the NCN6004A can independently handle the power
supply, in the range 2.7 V to 5.0 V input voltage, provided to each
external Smart Card. The interface monitors the current flowing into
each Smart Card, a flag being set in the case of overload.
Features
• Separated, Built-in DC/DC Converters Supply VCC Power to
External Cards
• 100% Compatible with ISO 7816-3, EMV and GIE-CB Standards
• Fully GSM Compliant
• Individually Programmable ISO/EMV Clock Generator
• Built-in Programmable CRD_CLK Stop Function Handles Run or
High/Low State
• Programmable CRD_CLK Slopes to Cope with Wide Operating
Frequency Range
• Programmable Independent VCC Supply for Each Smart Card
• Support up to 65 mA VCC Supply to Each ISO/EMV Card
• Multiple NCN6004A Parallel Operation on a Shared Bus
• 8 kV/Human Model ESD Protection on Each Interface Pin
• Provides C4/C8 Channels
• Provides 1.80 V, 3.0 V or 5.0 V Card Supply Voltages
Typical Applications
• Set Top Box Decoder
• ATM Multi Systems, POS, Handheld Terminals
• Internet E-commerce PC Interface
• Multiple Self Serve Automatic Machines
• Wireless Phone Payment Interface
• Automotive Operating Time Controller
http://onsemi.com
TQFP48
CASE 932F
PLASTIC
MARKING
DIAGRAM
NCN6004A
AWLYYWW
48
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
NCN6004AFTBR2 TQFP48 2000 Tape & Reel
© Semiconductor Components Industries, LLC, 2003
June, 2003 - Rev. 2
1
Publication Order Number:
NCN6004A/D
1 page  
NCN6004A
PIN DESCRIPTION (continued)
Pin Symbol
Type
10 RESET_A
INPUT
11 C4_A
INPUT
12 C8_A
INPUT
13 CLOCK_IN_A
Clock Input,
High Impedance
14 ANLG_GND
POWER
15 CLOCK_IN_B
Clock Input,
High Impedance
16 C8_B
INPUT
Description
The signal present on this pin is translated to the RST pin of the external smart card
#A. The CS signal must be Low to validate the RESET function, regardless of the
selected card.
Assuming the mP provides two independent lines to control the RESET pins, the
NCN6004A can control two cards simultaneously.
When MUX_MODE = High, this pin provides an access to either card A or B Reset
by means of CARD_SEL selection bit.
The associated pull up resistor is either connected to VCC (EN_RPU = H) or discon-
nected when EN_RPU = Low.
This pin controls the card #A C4 contact The signal can be either de-multiplexed, at
MPU level, or is multiplexed with C4_B, depending upon the MUX_MODE logic
state.
When MUX_MODE = High, this pin provides an access to either card A or B C4
channel by means of CARD_SEL selection bit.
The associated pull up resistor is either connected to VCC (EN_RPU = H) or discon-
nected when EN_RPU = Low.
This pin controls the card #A C8 contact. The signal can be either de-multiplexed, at
MPU level, or is multiplexed with C8_B, depending upon the MUX_MODE logic
state.
When MUX_MODE = High, this pin provides an access to either card A or B C8
channel by means of CARD_SEL selection bit.
The associated pull up resistor is either connected to VCC (EN_RPU = H) or discon-
nected when EN_RPU = Low.
The signal present on this pin comes from either the MCU master clock, or from any
signal fulfilling the logic level and frequency specifications. This signal is fed to the
internal clock selection circuit prior to be connected to the external smart card #A.
Each of the external card can have different division ratio, depending upon the state
of the CRD_SEL pin and associated programming bits. The built-in circuit can be
programmed to 1/1, 1/2, 1/4 or 1/8 frequency division ratio.
This input is valid and routed to either CRD_CLK_A _DIVIDER or CRD_CLK_B_DI-
VIDER regardless of the MUX_MODE state, depending upon the CLK_D_A/
CRD_D_B and CARD_SEL programmed states (Table 1).
Although this input supports the signal coming from a crystal oscillator, care must be
observed to avoid digital levels outside the specified VIH/VIL range. Similarly, the
input clock signal shall have rise and fall times compatible with the operating fre-
quency.
This pin is the ground reference for both analog and digital signals and must be con-
nected to the system Ground. Care must be observed to provide a copper PCB lay-
out designed to avoid small signals and power transients sharing the same track.
Good high frequency techniques are strongly recommended.
The signal present on this pin comes from either the MCU master clock, or from any
signal fulfilling the logic level and frequency specifications. This signal is fed to the
internal clock selection circuit prior to be connected to the external smart card #B.
Each of the external card can have different division ratio, depending upon the state
of the CRD_SEL pin and associated programming bits. The built-in circuit can be
programmed to 1/1, 1/2, 1/4, or 1/8 frequency division ratio.
This input is valid and routed to either CRD_CLK_B_DIVIDER or CRD_CLK_A_DI-
VIDER regardless of the MUX_MODE state, depending upon the
CRD_D_B/CRD_D_A and CARD_SEL programmed states (Table 1).
Although this input supports the signal coming from a crystal oscillator, care must be
observed to avoid digital levels outside the specified VIH/VIL range. Similarly, the
input clock signal shall have rise and fall times compatible with the operating fre-
quency.
This pin controls the card #B C8 contact. The signal can be either de -multiplexed,
at MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic
state.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is con-
nected to VCC (regardless of the logic state of EN_RPU is), and the access to card B
takes place by C8_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to VCC (EN_RPU = H) or discon-
nected when EN_RPU = Low.
http://onsemi.com
5
5 Page 
NCN6004A
POWER SUPPLY SECTION General test conditions, unless otherwise specified: Operating temperature: -25°C < TA < +85°C,
VCC = +3.0 V, CRD_VCC_A = CRD_VCC_B = +5.0 V. (continued)
Rating
Symbol
Pin
Min
Typ Max Unit
Output Card Supply Shut Off Time @
Cout = 10 mF, ceramic.
VCC = 2.7 V, CRD_VCC = 5.0 V, VCCOFF < 0.4 V (A or B)
VCCTOFF 31, 42
100 250
ms
DC/DC Converter Operating Frequency (A or B)
FSW
31, 42
5. Assuming ANLG_VCC and PWR_VCC pins are connected to the same power supply.
600
kHz
DIGITAL INPUT/OUTPUT SECTION
2.70 < VCC < 5.50 V, Normal Operating Mode (-25°C to +85°C ambient temperature, unless otherwise noted)
Rating
Symbol
Pin
Min
Typ
A0, A1, A2, A3, CARD_SEL, PWR_ON, PGM, CS, MUX_MODE,
EN_RPU, RESET_A, RESET_B, C4_A, C8_A, C4_B, C8_B
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
1, 2, 3,
4, 5, 6,
VIH 7, 8, 0.7 * Vbat
VIL 44, 45,
Cin 10, 18,
11, 12,
16, 17
STATUS, INT
Output High Voltage @ IOH = -10 mA
Output Low Voltage @ IOH = 200 mA
STATUS, INT
Output Rise Time @ Cout = 30 pF
Output Fall Time @ Cout = 30 pF
CLOCK_A Asynchronous Input Clock @ DC = 50% "1%
CLOCK_B Asynchronous Input Clock @ DC = 50% "1%
I/O_A, I/O_B, both directions @ Cout = 30 pF
I/O Rise Time
I/O Fall Time
STATUS Pull Up Resistance
INT Pull Up Resistance
I/O_A Pull Up Resistance
I/O_B Pull Up Resistance
RESET_A Pull Up Resistance
RESET_B Pull Up Resistance
C4_A Pull Up Resistance
C8_A Pull Up Resistance
C4_B Pull Up Resistance
C8_B Pull Up Resistance
CS Pull Up Resistance
CRD_DET_A and CRD_DET_B Pull Up Resistance
VOH
VOL
46, 47
Vbat –1.0 V
trsta, trint
tfsta, tfint
FCLKINA
FCLKINB
13
15
trioA, trioB
tfioA, tfioB
RSTA
RINT
RIOA
RIOB
RRSTA
RRSTB
RC4A
RC8A
RC4B
RC8B
RCS
RDETA
RDETB
9, 19
46
47
9
19
10
18
11
12
17
16
7
20
41
35
35
14
14
60
60
60
60
60
60
60
50
50
20
20
100
100
100
100
100
100
100
500
500
Max Unit
Vbat
0.3 * Vbat
10
V
V
pF
V
0.40
5 ms
100 ns
40 MHz
40 MHz
ms
0.8
0.8
kW
kW
35 kW
35 kW
kW
kW
kW
kW
kW
kW
kW
kW
kW
http://onsemi.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NCN6004AFTBR2.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NCN6004AFTBR2 | Dual SAM/SIM Interface Integrated Circuit | ON |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |